Effect of Light Illumination on Threshold Voltage and Sub-threshold Slope of Amorphous Silicon Thin Film Transistors

Abstract

AbstractIn this study the light induced defect state creation under 1 sun illumination is investigated through changes in sub-threshold slope, Δ, and threshold voltage, VT, in a-Si:H TFT structures. Threshold voltage changes can be due to either charge trapping or defect state creation near the interface of gate insulator and a-Si:H active layer. By incorporating high quality thermal silicon dioxide in the a-Si:H TFT, the charge trapping effects have been minimized and the changes in threshold voltage can be attributed to induced defect states in the a-Si:H. Since the sub-threshold current is closely related to the band gap defect states, both VT and Δ can be used as a new probe to study the light induced defect creation in the a-Si:H. The information obtained about the nature of gap defect states from the analysis of changes in VT and Δ under light illumination is presented. The results obtained show that under 1 sun illumination there are very fast increases (within 10 seconds) in VT with subsequent slow increases and no observable changes in Δ, similar to those observed in the light induced photoconductivity changes in a-Si:H thin films. The increase in VT under the initial light illumination are associated with the Fermi level in a-Si:H active layers moving downward and causing band bending near the interface region of the gate insulator and a-Si:H active layer. Results are also presented on changes in VT under gate-bias stressing. Comparisons are then made between the results obtained under 1 sun light illumination and those under gate-bias stressing. The information obtained in this study about the nature of the gap defect states derived from characterization of the sub-threshold regimes is discussed.