Polysilicon Emitter Bipolar Transistors Research Articles

Analysis and simulation of the current gain of polysilicon emitter bipolar transistors for low-temperature operation

An analytical current gain model of polysilicon emitter bipolar transistors for low-temperature operation based on the effective recombination method is presented. The model incorporates tunnelling of holes through the interface oxide layer, the reduced mobility mechanism, bandgap narrowing and carrier freeze-out effects. The low-temperature current gain and its temperature dependence are analysed numerically. The results agree well with experimental data.

Low frequency noise in polysilicon-emitter bipolar junction transistors

This paper describes experimental results on low frequency noise in several types of polysilicon-emitter NPN bipolar junction transistors. The experimental data were modelled using a combination of 1/f noise, generation-recombination noise (g-r), and shot noise, and good agreement between model calculations and experimental measurements were obtained. Observed differences in the experimental low frequency noise spectra of devices with similar geometry and under similar biasing conditions could be explained by the differences in the generation-recombination (g-r) noise contributions. Experiments were performed on devices with emitter areas varying from 1.6 to 144 μm2, and it was found that the magnitude of the flicker noise contribution KF varied inversely with emitter area AE or emitter perimeter PE. The fact that KF∼A−1E or KF∼P−1E is explained by the observation that AE∼PE within fabrication errors/tolerances. Using a set of 3.2 μm2 BJTs with pronounced g-r noise, input current noise was measured at different temperatures and from a deconvolution of the noise spectra, a trap at ∼400 meV and with a capture cross section of ∼4×10−17 cm2 was identified. Finally, the effect of different base implant and rapid thermal annealing conditions, polysilicon emitter thicknesses, and surface etching conditions on the noise magnitude were studied, and these results are also reported.

Study of RTS noise in degraded submicron polysilicon-emitter bipolar transistors

The random telegraph signal (RTS) noise is studied in the time domain on submicron area CMOS-compatible bipolar junction transistors after hot carrier stressing. The degradation, recovery and noise properties of the devices are discussed in terms of defect states located at/near the Si SiO 2 interface under the oxide spacer.

Low-frequency noise in polysilicon emitter bipolar transistors

The low-frequency noise in polysilicon emitter bipolar transistors is investigated. Transistors with various geometries and various properties of the oxide layer at the monosilicon polysilicon interface are studied. The main 1/f noise source proved to be located in the oxide layer. This source causes both 1/f noise in the base current S/sub Ib/ and 1/f noise in the emitter series resistance S/sub re/ The magnitude of the 1/f noise source depends on the properties of the oxide layer. The 1/f noise is ascribed to barrier height fluctuations of the oxide layer resulting in transparency fluctuations for both minority and majority carriers in the emitter, giving rise to S/sub Ib/ and S/sub re/ respectively. It is also shown that a low transparency of the oxide layer also reduces the contribution of mobility fluctuations to S/sub Ib/. >

Two-dimensional modeling of the enhanced diffusion in thin base n-p-n bipolar transistors after lateral ion implantations

Boron diffusion has been simulated in the context of a low thermal budget technology for thin-base integrated bipolar transistors. The simulation was performed using advanced physical models of diffusion, accounting for coupling with point defect diffusion. It has been found that in polysilicon emitter bipolar transistors, where the effect of the emitter implantation has the advantage of being suppressed, the excess point defects generated during the lateral extrinsic base implantations could still induce a nonnegligible broadening of the base and a shrinking of the active region. The influence of such parameters as the type of defects involved and their diffusion coefficient has been investigated. >

Technology and characterization of polysilicon emitter bipolar transistors for power applications

In order to increase the current gain via a reduction of the emitter-base junction saturation current density J SBE, a technological study of the fabrication of polysilicon emitter bipolar power transistors has been made. The wafer loading in the LPCVD furnace prior to polysilicon deposition and the substrate orientation affect the nature of the oxide formed at the polysilicon/monocrystal interface. In addition they have an effect on the emitter doping diffusion, thus modifying the measured electrical characteristics. The importance of the crystal quality of the collector epitaxy has been highlighted from the dynamic characterization and the determination of the J SBE values. For a blocking voltage of 600 V, a current gain of 80 at a J SBE value of 1.75 × 10 −13 A/cm 2 has been obtained.

Physical modelling of the enhanced diffusion of boron due to ion implantation in thin-base npn bipolar transistors

Using the most advanced physical models of diffusion, we have simulated boron diffusion in the context of a low thermal budget technology for thin-base integrated bipolar transistors. We demonstrated that simulation was able to account for the base broadening due to arsenic implantation in a monocrystalline emitter. Moreover, even in polysilicon emitter bipolar transistors, where the effect of the emitter implantation is suppressed, we found that the extrinsic base implantations could still induce a non-negligible base broadening.

Reduction of [formula omitted] noise in polysilicon emitter bipolar transistors

Polysilicon emitter bipolar transistors are becoming common in modern bipolar and BICMOS processes. For analogue applications, it is important to understand the noise phenomena as well as the more familiar circuit behaviour. In this paper we report on experimental studies of the 1 f noise in these transistors. Firstly, we show how the noise depends strongly on the type of interfacial oxide layer at the polysilicon/silicon interface. For example, the 10 Hz noise of a device with an RCA interfacial oxide layer is approximately four times higher than that of a comparable device with an HF interfacial layer (i.e. thinner and with poorer integrity). The dependence is explained by means of a simple mathematical model of the 1 f noise generation, based on the fluctuation in the occupancy level of individual traps in the thin oxide at the polysilicon/silicon interface. Two methods are presented for reducing the noise in polysilicon emitter bipolar transistors. The first involves the use of an interface anneal, which has the effect of breaking up the interfacial layer. This method reduces the 10 Hz noise by a factor of approximately four, but also dramatically reduces the current gain. The second method involves a fluorine implantation into the polysilicon immediately after the emitter implant. This reduces the 10Hz noise by a factor of approximately three, but does not significantly alter the current gain. This is explained by the action of the fluorine in passivating surface states in the interfacial oxide layer. It is also shown how the physical emitter structure can influence the noise. Both the effective depth of the emitter-base junction and the periphery-to-area ratio have an influence on the noise through the varying significance of surface recombination currents.

Low-frequency noise sources in polysilicon emitter BJT's: influence of hot-electron-induced degradation and post-stress recovery

The noise properties of polysilicon emitter bipolar transistors are studied. The influences of the various chemical treatments and annealing temperatures, prior and after polysilicon deposition, on the noise magnitude are shown. The impact of hot-electron-induced degradation and post-stress recovery on the base and collector current fluctuations are also investigated in order to determine the main noise sources of these devices and to gain insight into the physical mechanisms involved in these processes.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

An analytical model for determining carrier transport mechanism of polysilicon emitter bipolar transistors

An analytical model is proposed by including carrier transport mechanisms which previous unified analytical models do not consider: minority carrier combination at both sides of polysilicon-silicon interfacial oxides and thermionic emission over segregation potential barriers for determining the precise carrier transport mechanisms which govern current gain and specific emitter interfacial resistivity. This approach allows us to gain an insight into carrier transport mechanisms and provides a distinct image for polysilicon emitter bipolar devices. With the consideration of the interfacial capture cross section as a function of temperature, the dependence of current gain for devices given an HF etch prior to polysilicon deposition on temperature is first explained successfully. For improving device performance, some directive suggestions are presented. >

The benefits of fluorine in pnp polysilicon emitter bipolar transistors

BF/sub 2/ implantation into polysilicon and its subsequent rapid thermal diffusion into single crystal silicon is commonly used for the fabrication of pnp polysilicon emitter bipolar transistors. In this paper the effect of the fluorine, which is introduced into the polysilicon during the BF/sub 2/ implant, is investigated. Pnp polysilicon emitter bipolar transistors are fabricated in which the boron and fluorine are implanted separately, with the fluorine only going into one half of each wafer. Electrical results show that fluorine has two interrelated effects. In devices given a low thermal budget emitter drive-in, a drop in base current by a factor of approximately 3.2 is observed when the fluorine is present, together with an improvement in the ideality of the base characteristics. This is explained by the passivation of trapping states at the polysilicon/silicon interface by the fluorine. In contrast, in devices-given a higher thermal budget emitter drive-in, an increase in base current by a factor of approximately 2.5 is observed, when fluorine is present. This is explained by the action of the fluorine in accelerating the breakup of the interfacial layer. A model is proposed to explain this behavior.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Model and modeling of low temperature current gain of polysilicon emitter bipolar transistors

A unified model of low temperature current gain of polysilicon emitter bipolar transistors based on effective recombination method is presented, incorporating band-gap narrowing, carrier freezing-out, tunneling of holes through polysilicon/silicon interface oxide layer and reduced mobility mechanism in polysilicon. The modeling results based on this model are in good agreement with experimental data.

An Investigation of the Inconsistency in Barrier Heights for PNP and NPN Polysilicon Emitter Bipolar Transistors Using a New Tunneling Model

A new tunneling model is proposed for polysilicon emitter bipolar transistors in which the interfacial layer is modeled as a wide band-gap semiconductor. This model predicts that potential barriers are formed in both the conduction and valence bands. The shapes and sizes of the barriers are dependent upon the amount of band-bending within the interfacial layer, which is in turn dependent on the amount of dopant segregation in the interfacial layer. Measurements of base current and emitter resistance are made on pnp polysilicon emitter bipolar transistors with deliberately grown interfacial oxide layers. These electrical characteristics are then modeled using the new heterojunction tunneling model, from which values of electron and hole barrier heights are extracted. Specifically, a hole barrier height of 0.31±0.02 eV is obtained, and an electron barrier height of either >0.68±0.08 eV or >0.44±0.06 eV, with the value depending on the band-gap narrowing model used in the calculation. These values of electron and hole barrier height are shown to be different than the values obtained when similar measurements are made on npn devices. The new heterojunction tunneling model is used to model these devices, and it is shown that it is capable of fully explaining this discrepancy between the values of barrier height obtained from measurements on npn and pnp transistors.

A compact charge ratio expression for the emitter delay of polysilicon emitter bipolar transistors

A compact solution for the ratio of the excess minority carrier charge stored into the polysilicon to the charge stored in the single crystal part of the emitter of a polysilicon emitter bipolar transistor is derived. The solution is based on an existing comprehensive model which takes into account the interfacial oxide and an arbitrary number of grains in the polysilicon layer. The emitter charge partition in polysilicon and single crystal emitter components is summarized in contour plots for constant values of the ratio.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

A new parameter extraction technique for small-signal equivalent circuit of polysilicon emitter bipolar transistors

We propose a new parameter extraction method for advanced polysilicon emitter bipolar transistors. This method is based on the predetermination of equivalent circuit parameters using the analytical expressions of de-embedded Z-parameters of these devices. These parameter values are used as initial values for the parameter extraction process using optimization. The entire device equivalent circuit, containing RF probe pad and interconnection circuit parameters extracted by test structures, is optimized to fit measured S-parameters for eliminating de-embedding errors due to the imperfection of pad and interconnection test structures. The equivalent circuit determined by this method shows excellent agreement with the measured S-parameters from 0.1 to 26.5 GHz. >

High-low polysilicon-emitter SiGe-base bipolar transistors

Self-aligned heterojunction bipolar transistors with a high-low emitter profile consisting of a heavily doped polysilicon contact on top of a thin epitaxial emitter cap have been fabricated. The low doping in the single-crystal emitter cap allows a very high dopant concentration in the base with low emitter-base reverse leakage and low emitter-base capacitance. The thin emitter cap is contacted by heavily doped polysilicon to reduce the emitter resistance, the base current, and the emitter charge storage. A trapezoidal germanium profile in the base ensures a small base transit time and adequate current gain despite high base doping. The performance potential of this structure was simulated and demonstrated experimentally in transistors with near-ideal characteristics, very small reverse emitter-base leakage current, and 52-GHz peak f/sub max/, and in unloaded ECL and NTL ring oscillators with 24- and 19-ps gate delays, respectively. >

Impact of the emitter and base diffusion capacitances on the a.c. behavior of bipolar transistors

The influence of stored minority carrier charge in the emitter and base regions of a bipolar transistor on the small signal a.c. behavior is studied using small signal a.c. numerical simulation. The validity of the quasi-static approach to correctly model the contribution of the emitter diffusion capacitance to the small signal a.c. response, particularly in polysilicon emitter bipolar transistors, is assessed. It is shown that the onset of non-quasi-static behavior in the emitter of polysilicon emitter bipolar transistors can greatly reduce the impact of the emitter diffusion capacitance on the frequency response of the transistor. An analytic expression is presented which can model the impact of non-quasi-static effects in the emitter on the a.c. common emitter current gain, and which involves only quantities that can be obtained from a d.c. analysis.

Reliability imposed design aspects of submicrometer polysilicon-emitter bipolar transistors

The device reliability of narrow poly-emitter bipolar transistors with very shallow junctions is studied experimentally. The excess base current due to nonuniform poly doping, which is typically seen in such devices, is found not to accelerate device degradation. The lower doping at the emitter edge due to known perimeter depletion and emitter plug effects (PPEs) leads to a reduced increase in base current per perimeter length with stress. The results show that bipolar device scaling can probably be pursued to a point where PPEs start to appear, and that lateral emitter grading is effective in improving the device reliability. >

Influence of polysilicon deposition on fabrication of power polysilicon emitter bipolar transistors

The aim was to fabricate a polysilicon emitter bipolar transistor for power applications. To this end, different polysilicon deposition steps compatible with the power bipolar technology and their influence on electrical characteristics were studied.

Analytical and numerical studies of the dependence of high frequency performance on the use of a polysilicon emitter in bipolar transistors

The effects of the polysilicon emitter on the unity gain frequency ƒ T of bipolar transistors have been investigated both analytically and numerically. An analytical model for minority carrier transport in the polysilicon emitter that separately characterizes the polysilicon layer and the ultra thin oxide layer that could exist at the polysilicon/mono-crystalline silicon interface has been formulated. Using this analytical model as well as a one-dimensional numerical model, the presence of polysilicon grain boundaries was shown to degrade the high frequency performance of polysilicon emitter bipolar transistors with a clean interface as compared to that of conventional transistors with the same emitter-base junction depth. The interfacial oxide layer can either improve or degrade the transistor high frequency performance, depending on the thickness ratio of the mono-crystalline silicon emitter to the polysilicon emitter region. For a small ratio, the lower the tunnelling probability of the interfacial oxide layer the better is the improvement in ƒ T. However, if the ratio is larger the converse can be true. The thickness ratio at which the effect of the interfacial oxide layer on ƒ T reverses was foudn to depend primarily on the relative magnitudes of the minority carrier diffusion coefficients in the two emitter regions. It was also observed that for typical device designs where the mono-crystalline silicon emitter region is much thinner than the polysilicon emitter region and where a native interfacial oxide layer of ≥4 A ̊ exists, polysilicon emitter bipolar transistors are likely to have higher ƒ T's than comparable conventional transistors provided that the interfacial oxide layer is homogeneous.