Polycrystalline Silicon Thin Film Research Articles

Flexible TFT backplane development for extremely small bending radius with organic ILD and novel TFT structures

AbstractA new flexible low‐temperature polycrystalline silicon thin film transistors (LTPS TFTs) on PI substrate with organic ILD layer, island TFT, and TFT channel perpendicular to stress direction was proposed. AMOLED display panel manufactured with organic ILD did not show any visible degradation of panel image after outward rolling cycles of 200,000 at rolling radius of 4 mm or inward folding cycles of 200,000 at folding radius of 1 mm. Another novel structure of TFT with channel perpendicular to stress direction significantly reduced change of threshold voltage of −0.03 V compared with change of threshold voltage of −0.6 V for TFT with channel parallel to stress direction for reliability test of high drain current (HDC) after 100,000 outward‐bending cycles at bending radius of 3 mm. After inward‐bending cycles of 200,000 at bending radius of 1 mm, reliability test results for TFT device with organic ILD layer showed that change of on‐current is 10.07% for hot carrier instability (HCI) test, change of threshold voltage −0.31 V for negative bias thermal instability (NBTI) test, change of threshold voltage −0.24 V for hysteresis test, and breakdown voltage of gate insulator 7.73 MV/cm, respectively, and these performances are similar to those of TFT device with inorganic ILD (SiNx).

Roles of Trap States in the Dynamic Degradation of Polycrystalline Silicon Thin-Film Transistors Under AC Gate Bias Stress

Roles of Trap States in the Dynamic Degradation of Polycrystalline Silicon Thin-Film Transistors Under AC Gate Bias Stress

Effect of He diluted plasma on the deposition of flexible low-temperature polycrystalline silicon thin film

The growth of a low-temperature polycrystalline silicon (LTPS) thin film on a flexible polyethylene terephthalate (PET) substrate under the assistance of helium plasma has been examined in detail in this study. By utilizing the plasma enhanced chemical vapor deposition method, LTPS thin films are directly deposited on a PET substrate at a relatively low temperature (80 °C), and the variations in the morphology, structure, and electrical property of the samples with He flow are systematically characterized by performing a series of tests. The results show that the purely helium-diluted silane plasma has the function of inducing crystallization and fabricating the c-Si network. After optimizing the He flow rate to 600 SCCM, the LTPS thin film with the largest average grain size of ∼204.7 nm can be obtained, while the maximum dark conductivity (4.16 × 10−5 S/cm) is also achieved. Finally, a detailed discussion is presented to illustrate the growth mechanism of the LTPS thin film in He plasma.

High Reliability Tungsten-Doped Indium Zinc Oxide Thin Film Transistors for Display Applications

Recently, flat panel display technologies are based on amorphous silicon (a-Si), polycrystalline silicon (poly-Si) or amorphous oxide semiconductor (AOS) thin film transistors (TFTs) technology. In order to reach higher performance for ultra-high resolution display applications, the material selection for the channel layer is vital. AOS TFTs drawn lots of attention because of its advantages such as low leakage current, high driving current and high uniformity [1,3]. In this work, we presented a novel amorphous oxide semiconductor (AOS) material of gallium-free a-InWZnO thin film transistors (IWZO TFTs) which is very promising to be applied for ultra-high resolution display technology. Experiment In this work, we demonstrated the structure of a-IWZO TFTs processes. Figure 1 shows the schematic of the TFT cross-section. After growing a 550 nm thermal oxide layer as buffer layer, a 25-nm-thick of molybdenum was deposited by DC-sputter as the bottom gate electrode. A 10-nm-HfO2 was deposited by plasma-enhanced atomic layer deposition (PEALD) system as high-κ gate dielectric (GI). Then, post deposition annealing (PDA) was carried out to enhance the quality of the insulator layer. Next, an ultra-thin body a-IWZO was deposited by RF-sputter as channel layer. Finally, source and drain were defined by lift-off process and the gate contact via was etched by dry etching to finish the device fabrication. Result and Discussion Figure 1(b) shows the negative gate bias stress (NGBS) transfer curve (ID-VG) of a-IWZO TFTs with passivation layer. The experimental results have shown that passivation layer could keep the back channel of IWZO channel from exposing to oxygen and hydrogen from the atmosphere. Without the passivation layer, the back channel would contact moisture leading the diffused hydrogen atoms to fill oxygen vacancy sites and de-trap free carriers, causing the VTH shifts negatively. The ultra-thin a-IWZO TFTs with passivation layer exhibited a low subthreshold swing (S.S.) of 89.7 mV/dec, high on/off current ratio (ION/IOFF) of 2.1×107 and small threshold voltage shift (ΔVth) of -0.097 V during NGBS of -2MV/cm with 2000s. To sum up, the passivation layer could enhance the a-IWZO TFTs reliability. Reference [1] Kamiya, H. Hosono, NPG Asia Mater., vol. 2, pp. 15, 2010.[2] Nomura, H. Ohta, A. Takagi, T. Kamiya, M. Hirano, and H. Hosono, nature, vol. 432, no. 7016, pp. 488-492, 2004.[3] Y. Kuo, C. M. Chang, I. H. Liu, and P. T. Liu, Scientific reports, vol. 9, no. 1, pp. 1-7, 2019. Figure 1

Passivation of grain boundary electronic activity in polycrystalline silicon thin films by heat treatment and hydrogenation

Passivation of grain boundary electronic activity in polycrystalline silicon thin films by heat treatment and hydrogenation

Investigating DC and AC degradation behaviors to P-type low temperature polycrystalline silicon thin film transistor with fin-like structure

Currently, thin film transistor (TFT) based on planar structure is widely used in the applications of display panels. However, when the device is scaling-down, new device structures or novel materials should be introduced. In this work, the low temperature polycrystalline silicon (LTPS) TFT with fin-like structure is investigated. On the basis of electrical measurements, the device features good switching characteristics with low operating voltages. However, the I d–V g sweeping result exhibits off-state leakage, which is known as the gate-induced drain leakage (GIDL) current. The GIDL current is increased with the drain bias and the temperature increasing. To observe the GIDL current degradations, different gate biases with negative bias stress and positive bias stress are applied. The results show different degradation behaviors. In addition, bias stresses with DC and AC methods are also applied to verify the device reliability. Both threshold voltage (V t) shift and sub-threshold swing (S.S.) are also extracted to verify the degradations of the device. Finally, the physical models are also proposed to illustrate the degradation behaviors of the LTPS device with a fin-like structure, which can be beneficial to future related development of LTPS-based devices.

Self‐Regulating Process for Large Area Nanowire Solar Cells Based on Thin Polycrystalline Silicon Films Prepared on Glass

Herein, a process for the large‐area passivating and contacting of nanowire‐based solar cells is demonstrated. The nanowire‐based solar cells are prepared on layered laser crystallization (LLC) polycrystalline silicon (pc‐Si) thin films with thickness less than 2 μm. It is demonstrated that the space between the nanowires can be filled with a passivating dielectrics Al2O3 layer, and the nanowire tips can be exposed by a self‐regulating selective etching of the Al2O3 deposited on the tips and that on the sidewalls. The exposed tips of the nanowires can be connected by a transparent conducting aluminum‐doped zinc oxide (Al:ZnO or AZO) layer deposited by atomic layer deposition (ALD). The laser beam‐induced current mapping (LBIC) demonstrates that the current density can increase up to 63% at 633 nm due to light trapping and the superior passivation of the nanowires with an thin pc‐Si film of only 1.73 μm.

P‐11: A Novel AMOLED Pixel Circuit using Double‐Gate LTPO TFTs for Variable Refresh Rate with Low Power Consumption

This paper proposes an Active Matrix Organic Light Emitting Diode (AMOLED) pixel circuit for Variable Refresh Rate (VRR) driving from 1Hz to 240Hz. The circuit is based on a double‐gate Low Temperature Polycrystalline Silicon and Oxide (LTPO) Thin Film Transistor (TFT) backplane. For low frame rate driving we used oxide TFTs as the Switching (SW) TFTs. Moreover, we applied double‐gate Low Temperature Polycrystalline Silicon (LTPS) process to the Driving (DR) TFT for compensation of the Threshold Voltage (Vth) by controlling the bottom gate bias at a high refresh rate. In this paper, operation principle and simulation results will be illustrated to demonstrate the performance of the proposed circuit.

Impact of Nanosheet Thickness on Performance and Reliability of Polycrystalline-Silicon Thin-Film Transistors With Double-Gate Operation

Impact of Nanosheet Thickness on Performance and Reliability of Polycrystalline-Silicon Thin-Film Transistors With Double-Gate Operation

(Invited) Oxide TFT Applications: Principles and Challenges

The main advantage of the thin film transistor (TFT) is that it can be fabricated on non-wafer substrate independent of the size, flexibility, and morphology. All composing films of the TFT are deposited at the low temperature. Therefore, TFTs can be applied to a broad range of consumer, biological, chemical, and optical products that are difficult to fabricate with the wafer based MOSFETs.There are many reports on a-Si:H and poly-Si TFT applications in displays, imagers, sensors, drivers, flexible electronics, and circuits (1,2). In principle, oxide TFTs can be applied to similar products. However, since the device characteristics and compositing materials of the oxide TFT are different from those of the a-Si:H and poly- Si TFTs, as shown in Figure 1 and Table 1, there are advantages and disadvantages in former’s applications. In this presentation, oxide TFT applications in the following three areas will be discussed. Control of the attached device, such as pixel-driving in displays,Integrated circuits, such as drivers or inverters, andChanging of characteristics with environment, such as pH, optical, and temperature sensors. L. Antonuk, Chapt. 10, and Y. Kuo, Chapt. 11, Amorphous Silicon Thin Film Transistors, pp. 395-505, Kluwer Academic Publishers, 2004.B.-D. Choi, et al., Chapt. 11-13, Polycrystalline Silicon Thin Film Transistors, Y. Kuo Editor, pp. 360-495, Kluwer Academic Publishers, 2004.Kuo and G. W. Chang, ECS Trans, 64(10), 145-153 (2014). Figure 1

P‐1.4: Analysis of the Hump Characteristics in Poly‐Si Thin Film Transistor & Process a method to suppress hump effect

In this study, we investigate the transfer characteristics of low‐temperature polycrystalline silicon(LTPS) thin film transistors(TFTs) often show a “hump” in subthreshold region. This effect can be attributed to the presence of an enhanced electrical field at edges of the active layer. To reduce the hump effect which is one of the critical issues in ploy‐Si TFT, we focus on crowding of gate fringing field at channel edge and suggest a modified structure of channel edge. Using dry etching process, change the polysilicon layer at the edge of the channel from a steep profile to a slightly flat profile. And we confirmed that the severity of the hump effect is directly related to the edge profile of the polysilicon.

Modeling of High-Current Polycrystalline Silicon Thin Film Transistors by Incorporating Buried Electrode

For display applications, high current and large on/off current ratio are pursued for driving and switching transistors. In this article, a thin film transistor (TFT) device incorporating a buried electrode is proposed, which enables increasing the driving current by reducing the channel length, with the channel length only at the drain side. This lateral short-channel TFT enables increasing the on-current while maintaining the field effect mobility, in comparison to our experimental short-channel vertical TFT structure. Another advantage of the proposed structure lies in the suppression of the Schottky barrier at the source and drain contacts when using high-work-function source/drain contacts for an N-type TFT, with an increased on/off current ratio reaching approximately 106. The suppression of Schottky barrier at the source/drain has been verified by the contact resistance measurements. Even though high driving current is obtained, the off-current is still high due to the weakened electric field at the source/drain sides and needs to be further optimized.

Simplified EKV model parameter extraction in polysilicon MOSFETs

We present an easy but effective method to extract the four parameters of the simplified Enz–Krummenacher–Vittoz (sEKV) MOSFET model. The procedure, which is based on direct lateral optimization, is tested using measurements from experimental polycrystalline silicon Thin Film Transistors (TFTs) of various channel lengths and widths. We demonstrate that this basic MOSFET model is able to reasonably describe the saturation transfer characteristics of these polysilicon TFTs. Furthermore, we evaluate the computational adeptness for extracting the four sEKV parameters of the lateral optimization fitting procedure as compared to the more traditional vertical optimization one.

P‐32: Investigation on Mechanism of Illumination Mura in AMOLED Display with LTPS‐TFT Backplane after Long Term Localized Illumination

Low‐temperature polycrystalline silicon (LTPS) thin film transistors have been widely used in AMOLED display applications due to the high mobility and the capability of realizing peripheral and active matrix circuits on glass. Though LTPS TFTs exhibited relatively good electrical performance and stability, illumination Mura on AMOLED display with LTPS backplane could be observed by naked eye after several hours’ illumination on localized display area. The Mura boundary separates the areas with and without illumination when the AMOLED display is lighted on without pattern. The electrical instability of LTPS TFT was proved to be the main underlying cause. The DTFT threshold voltage compensation effect and SS variation in 7T1C pixel circuit has certain relationship with the illumination Mura detail.

14‐4: Enhanced Low Temperature Polycrystalline Silicon Thin‐Film Transistor Device Structure by Doping at Channel Edge

In this study, we propose a new low temperature polycrystalline silicon thin film transistor structure with good driving and reliability characteristics. The structure was proposed through TCAD simulation and verified through several simulation models. Thereafter, actual devices were manufactured to prove that characteristics were improved.

Characterization of Continuous-Wave Laser Crystallized Silicon Thin Films with Hole-Patterns

Single crystal grain low-temperature polycrystalline thin-film transistors (LTPS-TFTs) fabricated on a glass substrate have been the key target to develop transparent electronics such as monolithic three-dimensional integrated circuits (3DICs) and glass sheet computers because of their ultrahigh-performances. This study proposed a simple method to pre-define single-crystal grains with hole-patterned polycrystalline silicon (poly-Si) thin film. The crystal growth and the temperature distribution were clarified by observing the characterization of a hole-patterned poly-Si thin film. The relationship between the temperature gradient, crystal growth, and void formation in the poly-Si thin film was discussed. The location of voids was controllable in the hole-patterned poly-Si thin film. These pre-defined single-crystal grains are promising to fabricate ultrahigh-performance LTPS-TFTs.

Enhancing Reliability and 2 mm-Axial Mechanical Bending Endurance by Gate Insulator Improvements in Flexible Polycrystalline Silicon TFTs

In this study, the electrical performance and bending stress endurance of flexible low-temperature polycrystalline silicon thin film transistors (LTPS TFTs) are enhanced by increasing the helium concentration (1500 sccm) during gate insulator (GI) manufacture to create a high-quality GI device. Experimental results confirm that the subthreshold swing (S.S.) and mobility of these new &#x201C;high-flow&#x201D; devices are better than those with a lower helium concentration, which we term &#x201C;low-flow&#x201D; devices. The flow of helium gas is increased to achieve a better-quality oxide layer. The energy-dispersive X-ray spectroscopy (EDS) line data show a clear enhancement in oxygen content in the devices under this helium gas process. After mechanical compression and tensile bending stresses of 100000 iterations in the channel width-axis direction, perpendicular to the channel, with bending at <inline-formula> <tex-math notation="LaTeX">${R} = {2}$ </tex-math></inline-formula> mm, the modified GI devices with their more Si-O bond content exhibit less stress damage in the GI layer than do low-flow devices. As a result, this new manufacturing condition can effectively reduce the electrical degradation after negative-bias temperature stress (NBTS), and improve the overall electrical performance.

Strain distribution and electrical characteristics of flexible low-temperature polysilicon thin film transistors under biaxial bending

This paper investigates the strain distribution of flexible p-channel low temperature polycrystalline silicon thin film transistors under biaxial bending. The strain distribution of LTPS TFTs under different bending conditions is analysed by finite element analysis. \U0001d6c6r and \U0001d6c6θ are essentially equal and constant within the load ring. The finite element analysis shows that when the biaxial bending strain condition is 2.5%, the strain distribution is mainly concentrated at the contact angle between the electrode and the oxide layer. This strain is significantly greater than the overall strain of the device, which is the main reason for the bending performance of the device. We found that under biaxial bending, the threshold voltage shifts towards the negative axis as the biaxial strain increases. Within this strain range, these electrical properties are evident under biaxial strain conditions. Comparing theoretical threshold voltage shifts based on energy band changes with experimental results under biaxial strain, it was found that changes in trap density should also contribute to the threshold voltage shift.

Morphology and Conductivity Characteristics of Polycrystalline Silicon Thin Film Deposited by Plasma-Enhanced Vapor Deposition in Textured Substrate

We investigate the characteristics of polycrystalline Silicon (poly-Si) thin films for solar cells produced by very high frequency (VHF) plasma enhanced chemical vapor deposition using a conductive scanning probe microscope (SPM). We measure the surface morphology and local current images are simultaneously of the poly-Si layers with a thickness, d=2 mm, formed on textured Ag/SnO2/glass in the range of RMS based-textured substrate (a) s=85nm, (b) s=42nm and (c) s=2nm respectively. Influences of the substrate texture on the crystal growth as well as the local current flow are discussed. Where we found that the average of local current proportional with crystallinity, where the poly-Si layer that has rich crystallinity indicated low conductivity that yield high local current.

Effect of annealing temperature on the kinetics of aluminum-induced crystallization of amorphous silicon suboxide thin films

In this work, the kinetics of aluminum-induced crystallization (AIC) of non-stoichiometric silicon oxide a-SiO0.25 was investigated for the case of annealing at temperatures of 370, 385 and 400oC, as a result of which thin films of polycrystalline silicon were obtained. It is shown that, at low annealing temperatures, the surface morphology of the crystalline material is represented by dendritic structures corresponding to the growth model with diffusion-limited aggregation. In addition, with increasing annealing temperature, the nucleation density increases from 3 to 53 mm-2. From the Arrhenius plot, the activation energy of the a-SiO0.25 AIC was obtained for the first time and appeared to be 3.7± 0.4 eV. Keywords: aluminum-induced crystallization, silicon suboxide thin films, polycrystalline silicon, activation energy.