Polysilicon Plug Research Articles

Investigation of Detection Limits of Resistive Contact Plugs in Electron Beam Inspection Using Modeling and Simulation

<para xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> Electron beam inspection has been commonly used in the semiconductor fabrication process to inspect wafers for defective metal or polysilicon plugs, plugs that fail to make an electrical contact to the underlying circuitry. Recently, there has been interest in using electron beams to inspect plugs that are not necessarily electrically floating but have a high resistive path to ground. This paper addresses the reliability of such an inspection by examining the minimum resistance value that is detectable for a given column condition and gives guidelines for optimal inspection conditions for finding such a defective plug. The investigation is done using a transient simulation in a general purpose 3-D electron beam simulator that uses Monte Carlo simulations to trace the path of an ensemble of charged particles in an electrostatic field and couples with a general purpose Poisson solver that is also used to update the electrostatic fields from evolving charge profiles. </para>

Process compatible polysilicon-based electrical through-wafer interconnects in silicon substrates

Electrical through-wafer interconnects (ETWI) which connect devices between both sides of a substrate are critical components for microelectromechanical systems (MEMS) and integrated circuits (IC), as they enable three-dimensional (3-D) structures and permit new packaging and integration geometries. Previously demonstrated ETWI are very difficult to integrate with standard semiconductor fabrication processes, not compatible with released sensors, do not permit extensive processing on both sides of the wafer, and are in general very application specific. This work describes the design, fabrication, and characterization of an ETWI technology for silicon substrates that can be broadly integrated with MEMS and IC processes. This interconnect is a passively isolated electrical through-wafer polysilicon plug, with a 20 /spl mu/m diameter, 10-14 /spl Omega/ resistance, and less than 1 pF capacitance. Plasma etching from both sides of the wafer is used to achieve a high-aspect ratio via (20:1 through 400 /spl mu/m). The process is compatible with standard lithography, standard wafer handling, subsequent high-temperature processing, and released sensors integration. N-type and p-type versions are demonstrated, and isolated ground planes are added to provide shielding against substrate noise. Electrical properties of these ETWI are measured and analytically modeled. These ETWI are appropriate for integration with devices with impedances much greater than the ETWI, such as piezoresistive and capacitive sensor arrays.

Platinum contamination issues in ferroelectric memories

The contamination risk of processing with platinum electrodes on device performance in ferroelectric memories is assessed in this work. Details of platinum diffusion to the active regions at annealing temperatures of 800 °C are investigated by secondary ion mass spectroscopy, deep level transient spectroscopy, and Rutherford backscattering spectrometry techniques. Cross sectional transmission electron microscopy and local elemental analysis by energy dispersive x-ray spectroscopy were used to examine the precipitation of Pt in defect free silicon as an eventual cause of gate oxide degradation. The impact of platinum contamination on device performance is evaluated under the typical ferroelectric memory processing conditions. Results from leakage current and charge to breakdown measurements of intentionally contaminated diode and metal–oxide–semiconductor (MOS) structures, respectively, are presented. The results show that the degradation depends strongly on device design and configuration. A phosphorus doped polysilicon plug, which has the function of connecting the select transistor to the capacitor module, provides effective gettering regions and prevents the diffusion of Pt atoms to the active regions. Under typical processing conditions, no evident Pt precipitates were observed and up to a concentration level of 4×1014 atoms/cm2, the leakage current of intentionally contaminated diodes does not increase, if the contamination occurs after front-end phosphorus doped poly-Si processing. Results from constant current charge to breakdown show a small number of breakdown events due to redeposition of Pt at the periphery of the MOS structure. The risk of processing with Pt electrodes in ferroelectric memories requires great care. Precautions like sealing the back surface and incorporating phosphorus doped polysilicon as the plug material are necessary to avoid the detrimental effects of Pt.

Electrical properties of highly reliable plug buffer layer for high-density ferroelectric memory

A CoSi2 buffer layer was prepared in polycrystalline silicon (polysilicon) plug for preventing an undesired microvoid between the polysilicon plug and Ir/Ti diffusion barrier. Since the microvoid generates random function fail, resulting in low wafer yield of a 4 Mb ferroelectric random access memory device, we developed the thermally stable CoSi2 buffer layer for eliminating the random single bit fails. The ferroelectric capacitors using the CoSi2 buffer layer showed a low contact resistance of 96 Ω per contact in 1k serial contact array with contact size of 0.6 μm, and also exhibited great ferroelectric properties such as remnant polarization and coercive voltage of 20 μC/cm2 and 1.2 V, respectively. Scanning electron microscopy analyses confirmed that no microvoid was formed between the interface between the Ir/Ti barrier layer and the CoSi2 buffer layer.

Stacked Pt/SrBi2Ta2-xNbxO9/Pt/IrOx/Ir Capacitor on Poly Plug

A Pt/SrBi2Ta2-xNbxO9(SBTN)/Pt/IrOx/Ir capacitor was successfully fabricated up to the stage of metal-1 etching process on a polysilicon plug for mega-bit ferroelectric random access memory. The integration processes include the chemical-mechanical polishing technique, buried TiN barrier structure and electrode technologies for high thermal stability, and a low-temperature process for SBTN film. The thickness of the iridium layer was the most important factor in controlling the contact resistance of the plug. The Pt thickness also affected the contact resistance of the plug. The best contact resistance of the plug was about 2.0 kΩ/plug at the maximum process temperature of 750°C for 3 min in oxygen ambient at the contact size of φ0.30 µm. Hysteresis curves of the SBTN capacitor were obtained after the metal-1 etching process. The capacitor size dependency of the polarization was not observed in the range of 0.30–25 µm2 and the values of the sensing polarization were about 10 µC/cm2 at the applied voltage of 3 V. In addition, the capacitor exhibited no fatigue loss up to 5×1010 cycles at the switching voltage of 3 V.

Novel Chain Stack Capacitor for 32Mb FeRAM and Beyond

ABSTRACTFor high density FeRAM devices small cell sizes are essential. The combination of the capacitor on plug (COP) structure with the Chain FeRAM™ cell design is used to develop a 32Mb FeRAM. Based on a 0.2 μm standard CMOS process a silicide capped polysilicon plug is used to contact the bottom electrode of the ferroelectric capacitor to the transistor. The barrier contact to the plug is formed by IrO2/Ir and a sputter deposited PZT (40/60) is used as ferroelectric material. The function of SrRuO3 (SRO) layers at the electrode/PZT interfaces is described in more detail. Double sided SRO results in slightly lower coercive voltage and imprint behavior compared to capacitors without SRO. Double sided SRO is essential to achieve excellent fatigue behavior measured up to 1×1011 switching cycles.

Novel Electrode Barriers for High Density Ferroelectric Nonvolatile Memories

In this paper, we propose a new electrode-barrier structure for direct integration of lead zirconate titanate (PZT) based capacitors onto polysilicon plug for high density FRAM applications. The electrode-barrier structure is based on noble metal alloys (e.g. Pt–Rh, Pt–Ir, Pt–Ru) and their oxides (e.g. PtRhOx) which satisfy the needs for an excellent diffusion barrier as well as a high conducting electrode. It has been found that the PtRhOx/PtRh/PtRhOx electrode-barrier structure acts as a very good bottom electrode on poly-silicon plug. The bottom PtRhOx layer has shown excellent diffusion barrier properties for lead, oxygen and silicon up to processing temperatures of 700 °C as established by Auger electron spectroscopy and Rutherford backscattering spectroscopy studies. The electrode barriers showed no hillock formation and PZT films deposited on this structure crystallized predominantly in the perovskite phase. The capacitors exhibited very good hysteresis properties with remnant polarization (Pr) of 16 μC/cm2, a coercive field (Ec) of 32 kV/cm, extremely low fatigue (after 1×1010 cycles) of 3–4%, imprint (after 3.3×109 cycles) of 8–12%, retention (after 1×105 s) of 2–3% and leakage current density (at 100 kV/cm) less than 10—8 A/cm2. These electrode barriers hold excellent promise for application in high density FRAM capacitor over bit line (COB) structure.

Fabrication of mega-bit FeRAM with both stacked Pt/SBTN/Pt/IrOx/Ir capacitor and 0.25μm cmos design rule

Pt/SrBi2(Tai1-xNbx)2O9/Pt/IrOx/Ir capacitor was successfully fabricated up to metallization on poly silicon plug for Mega-bit FeRAM. The integration processes include CMP technique, buried TiN barrier structure and electrode technology for high thermal stability, low temperature process for SBTN film. The thickness of iridium layer was the most important factor in controlling the contact resistance of the poly silicon plug. Pt/IrOx thickness also affected the contact resistance. But the RTO treatment of the TiN barrier layer did not change the contact resistance. The best contact resistance of the plug was about 2kΩ/plug in the maximum process temperature of 750°C, 3min in oxygen ambient at the contact size of 0.30 Ωm in diameter. Hysteresis curves of the SBTN capacitor were obtained after metallization. The switching polarization was about 10μC/cm2, and capacitor size dependency of the polarization was not observed in the range of 0.30 μm2 ∼25 μm2

A novel diffusion barrier using oxygen stopping layer for high density FRAM

A novel diffusion barrier was successfully developed by using an oxygen stopping layer between Ir barrier films. The oxygen stopping layer was generated by inserting a Ti layer between Ir films, which results in the sandwiched form of Ir/Ti/Ir multi-layer. The diffusion barrier properties were enhanced by refraining oxygen from penetrating into polysilicon plug, which might be attributed to the reaction of oxygen with the Ir-Ti layer. It was confirmed in Auger depth profile that the oxygen was well localized in the stopping layer after annealing at 700°C for 10 min in O2 ambient. The multi-stack barrier exhibited low contact resistance of 320 and 650 ohm for contact size of 0.6×0.6 and 0.4×0.4 μm2, respectively. The PZT films prepared on Pt/IrO2/Ir-Ti-Ir/poly substrate shows remnant polarization of 20 μC/cm2 and coercive voltage of 1.2V at 5V. It was demonstrated that this novel barrier can solve barrier contact problem occurred in high density 16Mb FRAM.

Novel capacitor process using diffusion barrier rounded by Si/sub 3/N/sub 4/ spacer for high density FRAM device

A novel capacitor process was successfully implemented in 4 Mb FRAM device by developing a barrier layer rounded by Si/sub 3/N/sub 4/ spacer (BRS) scheme. Using this process, it is possible to eliminate an undesired barrier etching damage, which is a major role in degrading ferroelectric properties. The novel capacitor process was generated by etching an Ir barrier layer and rounding the barrier by a Si/sub 3/N/sub 4/ spacer before preparing Pb(Zr/sub 1-x/Ti/sub x/)O/sub 3/ (PZT) films. It was observed that uniform sol-gel derived PZT films were prepared on the patterned Ir substrate by using Si/sub 3/N/sub 4/ spacer, which provides a smooth edge of the patterned cell. The contact resistance between bottom electrode and polysilicon plug after full integration was monitored below 700 /spl Omega/ per contact with contact size 0.6/spl times/0.6 (/spl mu/m/sup 2/). Compared to the ferroelectric capacitor damaged by barrier etching, the novel Pb(Zr/sub 1-x/Ti/sub x/)O/sub 3/ (PZT) capacitor exhibited a well-saturated Q-V curve. The fully processed novel capacitor having 1.2/spl times/1.2 (/spl mu/m/sup 2/) effective area displayed remnant polarization of 14 (/spl mu/C/cm/sup 2/) at an operating voltage of 3.0 V. The BRS ferroelectric capacitor showed a reliable retention property until 100 h at 125/spl deg/C. Same state retention (Qss) was stable with time up to 100 h while opposite state retention (Qos) showed a log-linear decay rate at 125/spl deg/C thermal stress.

Integration and electrical properties of diffusion barrier for high density ferroelectric memory

A reliable Ir diffusion barrier was prepared on polysilicon plugged substrate with a contact size of 0.6 μm. Using a Ti adhesion layer and stress-relief process, it was possible to integrate the Ir barrier into a high density 4 Mb ferroelectric random access memory device. After heat treating sol-gel derived Pb(Zr1−xTix)O3 (PZT) films at 700 °C, the Ir barrier contact displayed an ohmic behavior and showed a low resistance of 130 Ω per contact in 1k serial contact array. The PZT films on Pt/IrO2/Ir poly-plugged substrate exhibited excellent ferroelectric properties such as remnant polarization and coercive voltage of 25 μC/cm2 and 1.15 V, respectively. Auger depth profile and transmission electron microscopy analyses confirmed that no appreciable oxidation was formed between the Ir barrier and the polysilicon plug.

High Temperature Barrier Electrode Technology for High Density Ferroelectric Memories with Stacked Capacitor Structure

This paper describes the novel stacked electrode structure, , applicable to stacked memory cells in advanced ferroelectric memories. This structure acts as a stable bottom electrode and a barrier on a polysilicon plug up to 700°C and a stable contact resistance of 1.5 KΩ is obtained at the contact size of 0.6 μm. In addition to the low leakage current of lead zirconate titanate ] capacitor (10−8 A/cm2 at 3 V), degradation properties of fatigue and imprint are improved compared with conventional Pt electrodes. The decrease of the switched charge is restricted to less than 10% after the fatigue cycle of 1011. These results indicate its promise as a barrier electrode structure for advanced ferroelectric memory integration.

Pt/TiN electrodes for stacked memory with polysilicon plug utilizing PZT films

Abstract The mechanism of TiN barrier metal oxidation of Pt/TiN electrodes are investigated for planarized stacked memory utilizing lead zirconate titanate (PZT). Thinner (<100 nm) and highly oriented platinum films are required in gigabit scale ferroelectric nonvolatile memories whose capacitor size is comparable to PZT grain size. Oxygen diffusivity to oxidize TiN is found to depend on the Pt film thickness. In cross-sectional TEM images of PZT/Pt/TiN/Si, titanium oxide is observed beneath the Pt grain boundary. The oxygen is diffused through the Pt grain boundary under heat treatment in an oxygen atmosphere for crystallization of PZT films, and oxidizes the underlying TiN barrier metal.

A new contact plug technique for deep-submicrometer ULSI is employing selective nickel silcidation of polysilicon with a titanium nitride stopper

A contact plug technique employing selective nickel silicidation of polysilicon with a titanium nitride barrier layer has been developed. This technique provides a contact resistance equal to that of an unplugged metal contact, while also realizing the flatness of a polysilicon plug over contact regions. Using this technique, a completely silicided plug for both shallow and deep contact holes can be achieved at the same time. The structure of the plug was analyzed using TEM photography, EDX, and electro-diffraction measurements, and the silicidation stopping ability of the TiN layer was confirmed. The low leakage current of junction diodes and lack of transistor characteristic degradation when using the Ni silicided plug are demonstrations of the integrity of this technique. The results indicate that this technology is suitable for deep-submicrometer ULSIs. >

Identification of perimeter depletion and emitter plug effects in deep-submicrometer, shallow-junction polysilicon emitter bipolar transistors

Two new types of narrow-emitter effects are identified in shallow and narrow-junction polysilicon emitter bipolar transistors. These effects result from a lower doping concentration close to the emitter perimeter of large devices (perimeter depletion effect) or in very-narrow-emitter devices where the polysilicon plugs up the emitter window (emitter plug effect). The consequence is a locally shallower emitter junction which causes a reduced collector current density and a nonideal base current due to a partial overlap of the emitter-base space-charge region with the poly/monosilicon interface. The nonuniform doping in the polysilicon is verified by energy-dispersive X-ray spectroscopy (EDX) measurements. Electrical measurements give a clear indication of the emitter plug effect for two different self-aligned transistor structures, and further evidence is given by a comparison of various poly emitter processes.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>