Polysilicon Gate MOSFET Research Articles

Ultra-Low Power Current Reference Based on Flat Band Difference of MOSFETs

In this paper, an ultra-low power MOS current reference circuit is presented. It is based on the flat band voltage difference of oppositely doped polysilicon gate MOSFETs which are operated in weak inversion. It describes a method to achieve zero temperature coefficient of reference current at target temperature. Simulation results show 20nA reference current with temperature drift of 165ppm/°C. Simulated 3σ monte carlo process and mismatch variation of current is 11.2nA. After trimming it is reduced to 808pA. Typical quiescent current is 22.5nA at 3.75V nominal supply voltage.

Two-dimensional semi-analytical model of subthreshold surface potential and drain current for double-doping polysilicon gate MOSFET

A semi-analytical subthreshold surface potential model for double-doping polysilicon gate (DDPG) MOSFETs is presented. By introducing two rectangular sources located in the gate insulator and the channel-depleted region, the two-dimensional (2D) Poisson equations are solved using a semi-analytical method combined with an eigenfunction expansion method. Expressions for the potentials are obtained as special functions of infinite series expressions. A subthreshold drain current is proposed on the basis of the potential profile, and it accounts for the carriers’ drift diffusion and thermionic emission theory. The advantage of this work is that the two-dimensional treatment of the gate insulator region has resulted in physical consistency across a dielectric boundary. The proposed model not only offers physical insight into device physics but also provides the basic designing guideline for DDPG MOSFETs, enabling the designer to optimize the device in accordance with the application. Very good agreement for both the subthreshold surface potential and drain current is observed between the model calculations and the simulated results.

Design of a novel double doping polysilicon gate MOSFET

In this paper, a novel design of the double doping polysilicon gate MOSFET device is proposed, which has a p+ buried layer near the drain, and relatively thicker D-gate oxide film (DDPGPD MOSFET). The detailed fabrication process for this device is designed using process simulation software called TSUPREM, and the device structure plan is further used in MEDICI simulation. The effect of gate doping concentration is investigated, and it is found that the device Vth is only influenced by the S-gate; furthermore, the device can get a larger driving current by increasing the doping concentration of D-gate. Compared to other conventional DDPG MOSFETs, the short-channel effects (SCEs) including the off-state current, the gate leakage current and the drain induced barrier lowering effect (DIBL) can be effectively suppressed by the p+ buried layer and thicker D-gate oxide film. Additionally, the other parameters of the device such as the driving current are not seriously affected by the proposed design modifications.

Design of Ion-Implanted MOSFET's with Very Small Physical Dimensions

This paper considers the design, fabrication, and characterization of very small MOSFET switching devices suitable for digital integrated circuits using dimensions of the order of 1μ. Scaling relationships are presented which show how a conventional MOSFET can be reduced in size. An improved small device structure is presented that uses ion implantation to proVide shallow source and drain regions and a nonuniform substrate doping profile. Onedimensional models are used to predict the substrate doping profile and the corresponding threshold voltage versus source voltage characteristic. A two-dimensional current transport model is used to predict the relative degree of short-channel effects for different device parameter combinations. Polysilicon-gate MOSFETs with channel lengths as short as 0.5μ were fabricated, and the device characteristics measured and compared with predicted values. Ibe performance improvement expected from using these very small devices in highly miniaturized integrated circuits is projected. Reprintedfrom the IEEE Journal of Solid-State Circuits, Vol. SC-9, October 1974, pp. 256-268.]

Influence of Image and Exchange-Correlation Effects on Electron Transport in Nanoscale DG MOSFETs

The impact of image and many-body exchange-correlation effects on electron transport has been investigated for nanoscale double-gate MOSFETs, using the nonequilibrium Green function method. The simulations have been performed for metal gate and polysilicon gate MOSFETs. When the gate material is metal, the inclusion of image and exchange-correlation effects increases the computed drain current, particularly at high gate voltages. In the case of polysilicon gate, the computed drain current remains almost unchanged at high gate voltages because both effects cancel out. However, at low gate voltages, the drain current is decreased by including these effects. In this study, the wavefunction penetration into the gate oxide and gate electrode has also been taken into account. Clear discrepancies between the drain currents calculated with and without considering the penetration effect can be found at low gate voltages. Further, the electron occupancy of each valley type is markedly changed by including this effect.

Self-aligned nickel, cobalt/tantalum nitride stacked-gate pMOSFETs fabricated with a low temperature process after metal electrode deposition

This letter reports the first replacement (Damascene) metal gate pMOSFETs fabricated with Ni/TaN, Co/TaN stacked electrode, where Ni or Co is in direct contact with the gate SiO/sub 2/, to adjust the electrode metal work function and TaN is used as the filling material for the gate electrode to avoid wet etching and CMP problems. The process is similar to the fabrication of traditional self-aligned polysilicon gate MOSFETs, except that in the back end (after the source/drain implants are activated) a few processing steps are added to replace the polysilicon with metal. Our data show that the Ni or Co/TaN gate electrode has the right work function for the pMOSFETs. The metal gate process can reduce the gate resistivity. Thermal stability of the stacked electrodes is studied and the result is reported in this paper. The damascene process flow bypasses high temperature steps (> 400/spl deg/C)critical for metal gate and hi k materials. This paper demonstrates that a low temperature anneal (300/spl deg/C) can improve the device performance. In this paper, the gate dielectrics is SiO/sub 2/.

Reexamination of the role of nitrogen in oxynitrides-fixed charge reduction in the p/sup +/-polysilicon gate MOS

The problems associated with the use of p/sup +/-polysilicon gate MOS have been intensively investigated. Although the utilization of oxynitrides has been considered to be effective for the suppression of the threshold voltage (V/sub T/) deviation in the p/sup +/-polysilicon gate MOSFETs, the investigation revealed that the p/sup +/-polysilicon gate MOS exhibits significantly different properties when oxynitrides contain no nitrogen at the oxynitride/substrate interface (MOS interface) than it does with usual oxynitrides which contain nitrogen at the MOS interface. This discrepancy arises because, contrary to what is usually considered to be the case, boron diffused into the substrate is not the origin of the negative fixed charge generated in the p/sup +/-polysilicon gate MOS structures, which is one of the most important factors influencing VT in those structures. We have found fluorine in the p/sup +/-polysilicon gate MOS structures even when the polysilicon is doped using boron ion implantation. This is a consequence of the use of BF/sub 3/ as a boron source. We propose a model in which fluorine is responsible for the negative fixed charge generation and nitrogen at the MOS interface prevents not only the boron penetration but also the negative fixed charge generation by suppressing the fluorine incorporation into the MOS interface.

Simulation study on comparison between metal gate and polysilicon gate for sub-quarter-micron MOSFETs

Two-dimensional (2-D) process and device simulation is used to investigate the effectiveness of the depletion-free metal gate for a sub-quarter-micron MOSFET as compared with surface channel polysilicon gate MOSFETs which suffer greatly from the gate depletion effect. The results reveal that the subthreshold characteristic for the metal gate NMOSFET is considerably degraded since the depletion-free merit is covered up by an undesirable influence of the buried channel structure, which is indispensable to obtain an appropriate threshold voltage for the midgap gate. Consequently, the drivability of the metal gate MOSFET is comparable to that of the heavily doped polysilicon gate MOSFET under commonly used conditions, and further, the metal gate structure is disadvantaged against the reduction of the supply voltage.

Scaling of maximum capacitance of MOSFET with ultra-thinoxide

The maximum capacitance of a polysilicon-gate MOSFET against oxide thickness is studied for different gate and substrate doping levels. It is found that substrate doping contributes to transistor capacitance degradation, imposing a limit on the lower voltage operation for sub-0.1 µm CMOS technologies.

SiGe-channel n-MOSFET by germanium implantation

The first n-SiGe-channel MOSFETs fabricated using high-dose germanium implantation and solid-phase epitaxy are reported. The polysilicon-gate MOSFETs were fabricated in the same chip in which conventional polysilicon-gate n-MOSFETs were made and their electrical characteristics are compared. The SiGe-channel MOSFETs show some significantly better electrical characteristics as compared to the silicon-channel MOSFETs. For example, the SiGe MOSFETs show higher drain conductance in the triode region and higher transconductance overall. The threshold voltage of the SiGe MOSFET appears to be smaller and the carrier mobility in the channel appears to be higher.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

A comprehensive study on p/sup +/ polysilicon-gate MOSFET's instability with fluorine incorporation

It is reported that fluorine can jeopardize p/sup +/-gate devices under moderate annealing temperatures. MOSFETs with BF/sub 2/ or boron-implanted polysilicon gates were processed identically except at gate implantation. Evidence of boron penetration through 12.5-nm oxide and a large quantity of negative charge penetration (10/sup 12/ cm/sup -2/) by fluorine even at moderate annealing conditions is reported. The degree of degradation is aggravated as fluorine dose increases. A detailed examination of the I-V characteristics of PMOSFET with fluorine incorporated p/sup +/-gate revealed that the long gate-length device had abnormal abrupt turn-on I/sub d/-V/sub g/ characteristics, while the submicrometer-gate-length devices appeared to be normal. The abnormal turn-on I/sub d/-V/sub g/ characteristics associated with long-gate-length p/sup +/-gate devices vanished when the device was subjected to X-ray irradiation and/or to a high-voltage DC stressing at the source/drain. The C-V characteristics of MOS structures of various gate dopants, processing ambients, doping concentrations, and annealing conditions were studied. Based on all experimental results, the degradation model of p/sup +/-gate devices is presented. The incorporation of fluorine in the p/sup +/ gate enhances boron penetration through the thin gate oxide into the silicon substrate and creates negative-charge interface states. The addition of H/OH species into F-rich gate oxide will further aggravate the extent of F-enhanced boron penetration by annealing out the negative-charge interface states. >

Correlation of G/sub m/ degradation of submicrometer MOSFETs with refractive index and mechanical stress of encapsulation materials

Evaluations of five different plasma-deposited silicon nitride films for use as an encapsulation material for polysilicon-gate MOSFETs are discussed. The films were (1) a-SiN:H; (2) Applied Materials a-SiN:H process B; (3) Applied Materials a-SiN:H process D; (4) silicon oxynitride, a-SiON:H; and (5) fluorinated silicon nitride, a-SiNF:H. Submicrometer MOSFET devices that aged the least as measured by transconductance degradation were encapsulated with films having the lowest refractive index (a-SiON:H and a-SiNF:H). The results show that films with low refractive index and low absolute value of mechanical stress age the least. The results are interpreted in terms of the Meyer-Fair model where the lower refractive index films are more porous to H leaving the device than the higher refractive index films. >

Novel self-aligned polysilicon-gate MOSFETs with polysilicon source and drain

A novel self-aligned technique is described for self-aligning a polysilicon gate in devices with polysilicon source and drain regions. The technique is demonstrated for two types of polysilicon source and drain devices. In one type of device, the polysilicon serves as the source of dopant for diffused source and drain junctions. In the second type, the polysilicon, together with an underlying interfacial oxide, forms a tunneling CIS (conductor-thin insulator-semiconductor) structure. The characteristics of devices of both types fabricated under almost identical conditions using the new self-alignment technique are compared.

Selective silicon epitaxial growth for device-isolation technology

Selective silicon epitaxial growth using the SiH 2 Cl 2/ HCl/ H 2 system under reduced pressure was accomplished in windows surrounded by a fine patterned insulator film on a silicon substrate. Selectivity, surface planarity, and facet formation were studied as a function of growth pressure, growth temperature, and HCl flow rate during selective epitaxial growth. Defects, which were mostly pairs of stacking faults, were observed along sidewalls. The defect density in the epi-layer decreased with both decreasing growth temperature and increasing HCl flow rate. Electrical properties of p-n junctions fabricated in the epi-layers were investigated. Polysilicon gate MOSFETs were successfully fabricated on the epitaxial silicon layers. It was revealed that the selective epitaxial growth isolation was effective to reduce latch-up susceptibility for CMOS circuits. It has been discovered that the selective epitaxial growth is applicable to fine and deep isolation and can realize submicron geometry isolation for VLSI.

Novel device isolation technology with selective epitaxial growth

A novel device isolation technology for small geometry VLSI's using selective epitaxial growth is described. This isolation structure is composed of an SiO <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf> insulator and an epitaxial silicon selectively grown on a bulk silicon surface surrounded with an SiO <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf> isolation wall using a reduced pressure SiH <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf> Cl <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf> -H <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf> -HCl system. This technology, called SEG (selective epitaxial growth) isolation, offers the potential of both fine and deep isolation with submicrometer size features. Polysilicon gate MOSFET's are successfully fabricated on the epitaxial silicon layer. The subthreshold slopes for p-channel or n-channel devices are confirmed to be consistent with these for conventional devices. Using SEG isolation technology, less channel width variation and small narrow-channel effect are shown by electrical characteristics for MOSFET's. The subthreshold behavior for parasitic field devices with submicrometer geometry gives results applicable to fine isolation.

A new aluminum pattern formation using substitution reaction of aluminum for polysilicon and its application to MOS device fabrication

This paper describes a new aluminum pattern formation process using the substitution reaction of aluminum for polysilicon (APSP), and its application to the fabrication of self-aligned aluminum-gate MOSFET's. The APSP method uses the intensive interdiffusion reaction between aluminum and polysilicon observed for contact structure where the aluminum film overlaps polysilicon and is heat treated below the eutectic temperature (577°C). The basic idea in the fabrication of self-aligned aluminum-gate MOSFET's using APSP is to replace the polysilicon gate with an aluminum gate in the final step following fabrication of the self-aligned polysilicon-gate MOSFET. It is shown that the new fabrication process can be followed by almost all of the conventional polysilicon-gate processes. It is also shown that the electrical characteristics of the aluminum-gate MOSFET fabricated using APSP are nearly the same as those of polysilicon-gate MOSFET's fabricated on the same wafer.

Dominant subthreshold conduction paths in short-channel MOSFET's

Conduction modes in off-biased n <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> -polysilicon gate MOSFET's of both polarities have been analyzed by two-dimensional device simulations. It was found that the dominant leakage paths in p-channel and n-channel enhancement devices occur in the bulk and at the surface, respectively, at <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V_{GS} = V_{BS} = 0</tex> . The control of these two distinct modes is the flatband voltage of the gate. The situation is exactly reversed when boron-doped polysilicon is used as the gate. Additionally, we showed that this physical insight can be readily gained by a quasi-two-dimensional analysis of the surface potential and its bending into the substrate. The leakage mode in short-channel MOSFET's with other gate material or with different interface properties generated by radiation or other stresses can thus be easily assessed. Subthreshold characteristics have been simulated for n <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> -polysilicon-gate low-threshold p-channel transistors having a p-type surface from boron counterdoping. The computed channel-length dependence is found to be in good agreement with measured data. Dominant leakage paths, in this case, remain in the bulk, while the surface holes from boron counterdoping are depleted by the flatband voltage. Since the common practice for reducing subthreshold leakage is to enhance substrate impurity concentration where punchthrough occurs, we therefore conclude that different strategies of process tailoring are required for MOSFET's of different gate material, surface polarity, and interface properties.

Self-Aligned Phosphorus Doped Polysilicon Gate MOS Device Radiation Hardening

It is well known that processing steps strongly affect the radiation tolerance of MOS oxides. In this paper we present the effects of the ion implantation to form the source-drain regions of self-aligned polysilicon gate MOSFETs. Radiation hardness varies systematically with the n+ and the p+ ion implantation energies, and the masking polysilicon gate thickness. For a fixed polysilicon thickness, there is an optimum implantation energy allowed to give the best device performance and radiation behavior. Extending the implantation energy beyond the optimum tends to degrade the hardness. This is verified by the capacitor experiments. The shift in n-channel threshold for devices fabricated by the optimum radiation-hardened process developed here is decreased from -6.1V to -1.8V at 3 × 105 rads (Si) total dose. The p-channel threshold at 1 × 106 rads (Si) is decreased by 4.5 volts. The 8-bit Arithmetic Logic Unit (ALU) device from wafer to wafer, and lot to lot can be operated well up to 1 × 106 rads (Si).

WP-A3 Application of CW argon laser annealing on fabricating short-channel PolySilicon-gate MOSFET's

WP-A3 Application of CW argon laser annealing on fabricating short-channel PolySilicon-gate MOSFET's

Annealing of radiation-induced positive charge in MOS devices with aluminum and polysilicon gate contacts

This paper discusses the removal of radiation-induced positive charge from MOS structures by low temperature thermal anneals. Results are presented for structures in which the gate oxide is covered either by an aluminum or by a polysilicon contact during the anneal. The anneals were performed in forming gas, nitrogen and hydrogen ambients. The presence of aluminum over the gate oxide is found to play an important role in the annealing of radiation-induced positive charge in these structures . While a 400‡C anneal is sufficient to remove this charge from capacit or structures with aluminum gates, it leaves a small amount of residual charge (about 6xl010}cm2}) in structures with polysilicon gates. Anneals at temperatures in excess of 550‡C are required to remove this charge completely from the polysilicon-gated MOS devices. However when a thin layer of aluminum is present over the polysilicon contact during the anneal the charge can be removed easily at 400‡C. The results in capacitor structures are consistent with those found in polysilicon gate MOSFET’s with similar coverage over the gate oxide.