Self-Aligned Phosphorus Doped Polysilicon Gate MOS Device Radiation Hardening

Abstract

It is well known that processing steps strongly affect the radiation tolerance of MOS oxides. In this paper we present the effects of the ion implantation to form the source-drain regions of self-aligned polysilicon gate MOSFETs. Radiation hardness varies systematically with the n+ and the p+ ion implantation energies, and the masking polysilicon gate thickness. For a fixed polysilicon thickness, there is an optimum implantation energy allowed to give the best device performance and radiation behavior. Extending the implantation energy beyond the optimum tends to degrade the hardness. This is verified by the capacitor experiments. The shift in n-channel threshold for devices fabricated by the optimum radiation-hardened process developed here is decreased from -6.1V to -1.8V at 3 × 105 rads (Si) total dose. The p-channel threshold at 1 × 106 rads (Si) is decreased by 4.5 volts. The 8-bit Arithmetic Logic Unit (ALU) device from wafer to wafer, and lot to lot can be operated well up to 1 × 106 rads (Si).