Abstract
A novel device isolation technology for small geometry VLSI's using selective epitaxial growth is described. This isolation structure is composed of an SiO <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf> insulator and an epitaxial silicon selectively grown on a bulk silicon surface surrounded with an SiO <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf> isolation wall using a reduced pressure SiH <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf> Cl <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf> -H <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf> -HCl system. This technology, called SEG (selective epitaxial growth) isolation, offers the potential of both fine and deep isolation with submicrometer size features. Polysilicon gate MOSFET's are successfully fabricated on the epitaxial silicon layer. The subthreshold slopes for p-channel or n-channel devices are confirmed to be consistent with these for conventional devices. Using SEG isolation technology, less channel width variation and small narrow-channel effect are shown by electrical characteristics for MOSFET's. The subthreshold behavior for parasitic field devices with submicrometer geometry gives results applicable to fine isolation.
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