poly-Si TFT Research Articles

Hardware-Based Ternary Neural Network Using AND-Type Poly-Si TFT Array and Its Optimization Guideline

Hardware-Based Ternary Neural Network Using AND-Type Poly-Si TFT Array and Its Optimization Guideline

TCAD Simulation of the Electrical Characteristics of Polycrystalline Silicon Thin Film Transistor


 Low-temperature polycrystalline silicon thin film transistors (poly-Si TFTs) have been studied because of their high performance in Active Matrix Liquid Crystal Displays (AMLCD's) and Active Matrix Organic Light-Emitting Diode (AMOLED) applications. The purpose of this work is to simulate the impact of varying the electrical and physical parameters (the interface states, active layer's thickness and BBT model) in the transfer characteristics of poly-Si TFT to extract the electrical parameters like the threshold voltage, the mobility and to evaluate the device performance. The device was simulated using ATLAS software from Silvaco, the results show that the electrical and physical parameters of poly-Si TFT affect significantly its transfer characteristics, choosing suitable parameters improve high-performance transistor. Such results make the designed structure a promising element for large-scale electronics applications.
 
 

Poly-Si Finlike Thin-Film Transistors With Various Wide Drain Designs for Radio Frequency and 3-D Integrated Circuits

The dc and high-frequency performance of p-type polycrystalline silicon (poly-Si) finlike thin-film transistors (FinTFTs) with various wide drain region designs are investigated herein. The poly-Si FinTFT with the triangular wide drain design exhibits a high $I_{\text{ON}}/I_{\text{OFF}}$ current ratio ( ${f}_{\text {T}}\boldsymbol {=} {371.5}$ MHz at ${V}_{\text {DS}}\boldsymbol {=-}{1}$ V). This structure has lower drain series resistance ${R}_{\text {d}}$ than does the conventional poly-Si FinTFT and lower gate-to-drain capacitance ${C}_{\text {gd}}$ than does the poly-Si FinTFT with the hybrid wide drain design. This result indicates the possible use of poly-Si TFT technology for radio frequency integrated circuits and the great potential for future use in 3-D integrated circuits.

High Speed and Wider Swing, Level Shifter Using Low-Temperature Poly-Silicon Oxide TFTs

We report the CMOS level shifter (LS) made of p-type low-temperature poly-Si (LTPS) TFT using blue laser annealing (BLA) of amorphous Si (a-Si) and an n-type amorphous indium-gallium-zinc oxide (a-IGZO) TFT. Two cascaded inverters with the bootstrap capacitor are utilized. 1- clock signal and 2- supply voltage are employed to obtain a full output swing from high output voltage to ground. For an input swing of (2–10) V, the proposed LS shows a shifted output swing of (10–30) V. Having the fast rise time of 688 ns, it operates in the broad clock frequency range of 1 ~ 500 kHz. The operating clock frequency, ‘rail-to-rail’ level shifting and faster rise time confirm its superiority.

A Low Impact Ionization Rate Poly-Si TFT with a Current and Electric Field Split Design

In this study, a novel low impact ionization rate (low-IIR) poly-Si thin film transistor featuring a current and electric field split (CES) structure with bottom field plate (BFP) and partial thicker channel raised source/drain (RSD) designs is proposed and demonstrated. The bottom field plate design can allure the electron and alter the electron current path to evade the high electric field area and therefore reduce the device IIR and suppress the kink effect. A two-dimensional device simulator was applied to describe and compare the current path, electric field magnitude distributions, and IIR of the proposed structure and conventional devices. In addition, the advantages of a partial thicker channel RSD design are present, and the leakage current of CES-thin-film transistor (TFT) can be reduced and the ON/OFF current ratio be improved, owing to a smaller drain electric field.

Investigation of Parasitic Resistance Components in the Case of Microwave Irradiation in Poly-Si Annealing

We fabricated transmission-line method (TLM)-type devices for analysis of the interface uniformity between an aluminum electrode and n-type silicon by using phosphorus implantation. For the dopant activation, we adopted novel microwave irradiation (MWI) as an alternative to rapid thermal annealing (RTA). Also, we investigated the contact resistance (RC), sheet resistance (RS), transfer length (LT) and specific contact resistance (ρC) that affected the thin-film transistor’s (TFT’s) performance through the TLM, and we compared parameters for various annealing methods. MWI showed a RC (2.175 Ω) which is similar to that for RTA (1.825 Ω). Also, MWI resulted in improved LT and ρC (4.426 μm, 0.48×10−4 Ω·cm2, respectively) characteristics compared to RTA (8.238 μm, 0.752 × 10 −4 Ω·cm2, respectively). Consequently, MWI, which has a lower thermal budget showed improved uniformity compared to RTA, and the total processing time was lower. Thus, we expect the MWI method to be an excellent choice for high-performance poly-Si TFT applications and to have various advantages.

Low-temperature poly Si TFTs via BLDA for a Ne-sputtered Si film using sputtered gate SiO2

ABSTRACTAmorphous SiO2 and amorphous Si films were deposited on glass using radio frequency (RF) sputtering, and were subsequently poly-crystallized using blue-laser diode annealing (BLDA) scanned by a CW beam. Ne, which has a smaller atomic radius than Ar, was used for the sputtering of the Si film. For the gate insulator, a small amount of O2 gas diluted with Ar was flown during the sputtering to optimize the SiO2 film with a low leakage current. A simple TFT structure with a metal source and drain (S/D) was adopted to realize a low-temperature process with a low fabrication cost. Furthermore, to confirm the effectiveness of the sputtered gate oxide, a poly-Si TFT adopting a Si film deposited using plasma-enhanced chemical vapor deposition (PE CVD) for the channel was fabricated and was compared with the TFT with a sputtered Si film for the channel. Reasonable Vg-Id characteristics were obtained for both poly-Si TFTs. The TFT structure with a metal S/D formed through a low-temperature sputtering-based process is expected to be applied to Si TFTs on an arbitrary flexible panel.

(Invited) Technology Trend of Poly-Si TFT from Viewpoints of Crystallization and Device Performance

TFTs utilizing the Low-Temperature Polycrystalline-Si (LTPS) are very crucial for the system-on-glass. The requirements for the LTPS are a high quality, a large grain size and a position control of the nucleation. To satisfy those requirements, the promising crystallization methods have been presented. In addition, the device structures such as the double gate TFT and the tunnel type TFT have been developed. The excimer laser annealing provided a large grained film with a high-quality. It was also clarified that hydrogens in a-Si film greatly accelerated the crystal velocity and improved the crystallinity of the poly-Si film. A soft X-ray crystallization (SXC) reduced the threshold temperature of crystallization for a-Si, Ge and SixGe1-x films by 100-150 oC as compared with the thermal crystallization. Although the high-performance TFT utilizing the large single crystalline grains has been intensively researched, it does not successfully operate from the productive viewpoint. Tunneling Dielectric Thin-Film Transistor (TDTFT) was proposed and fabricated. It reduced the gate-off current less than 1/10 in comparison with a conv. TFT. In addition, the TDTFT improved the hump effect. We conclude that TDTFT will be suitable as a promising candidate of the next generation poly-Si TFT structure.

57‐2: Scalable Crystallization of a‐Si Film on a Glass Substrate by Using a Blue Laser

A continuous-wave blue laser annealing (BLA) system (λ ~ 440 nm) is applied to delineate the physical phenomenon of low-temperature crystallization from amorphous Si (a-Si) thin film to poly-Si film on glass substrates for potential industrial application. At various scanning speeds and laser intensities, crystallization mechanism of BLA has been studied. It shows that BLA can achieve high quality, smooth poly-Si film with laterally grown grains with sizes of 4×10 µm, as studied by optical microscopy, Raman spectroscopy, and AFM. The p-channel poly-Si TFT on glass exhibited the field-effect mobility of 120.82 cm2/Vs and subthreshold swing of 284mV/dec. Therefore, it proves that BLA can substitute conventional annealing processes as a reliable, scalable, and economical tool.

Quantitative Analysis of Deuterium Annealing Effect on Poly-Si TFTs by Low Frequency Noise and DC ${I}$ – ${V}$ Characterization

Deuterium (D <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> ) annealing was applied to a poly-crystalline silicon thin-film transistor (poly-Si TFT) to improve reliability and performance. The field-effect electron mobility (μ) was extracted using the gate transconductance (g <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m</sub> ) method. It was found that μ was improved before and after D <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> annealing. The interface trap density (D <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">it</sub> ) as well as the oxide trap density (N <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ot</sub> ) in the poly-Si TFTs was quantitatively extracted using both conventional dc I-V characterization and analysis of low frequency noise (LFN). The profile of N <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ot</sub> along the depth direction was investigated before and after D <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> annealing using LFN characteristics. It was confirmed that D <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">it</sub> as well as N <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ot</sub> was reduced by the D <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> annealing, resulting in a reduction in power spectral density and variation.

35.1: Blue-Diode Laser Annealing of Amorphous Silicon Films for Low-Cost, Large-Scale Manufacturing of Advanced Displays

Blue diode laser annealing (BLA) systems have been successfully developed for low-temperature crystallization from amorphous silicon film on glass substrates. It is demonstrated that it can achieve high quality poly-Si film with large grain sizes, as studied by optical microscopy, Raman spectroscopy and AFM measurements. The p-channel poly-Si TFT on glass using BLA exhibited the field-effect mobility of 168.05 cm2/Vs and subthreshold swing of 220 mV/dec. BLA is scalable to large-scale display manufacturing and significantly lowers the capital expense and operating cost, since diode lasers are highly reliable and rugged, remarkably efficient, and maintenance-free, allowing 24/7 operations without the need of consumables. The BLA system consists of an array of high-power blue diode lasers (λ ~ 450 nm) and beam-shaping optics to produce a line-shaped beam which can be scanned at high speed to anneal the Si film in a single scan, where the high scan speed minimizes thermal stress. The scan-to-scan is seamless to cover a large panel such as G6 or G8 without glass damage. The physical phenomena responsible for melting and recrystallization are explained by heat transfer simulations for process optimization.

A Hybrid Wide Drain Poly-Si FinTFT for RF Application

In this paper, a hybrid wide drain polycrystalline silicon (poly-Si) fin-like thin-film transistor (FinTFT) for radio frequency (RF) applications is fabricated. A high $I_{\mathrm {ON}}/I_{\mathrm {OFF}}$ current ratio (>108) and favorable gate control (SS = 198 mV/dec) are observed, and a high cutoff frequency ( $f_{T} =9.55$ GHz @ $V_{\text {DS}}=1$ V and 12.45 GHz @ $V_{\text {DS}}=2$ V) is achieved. The hybrid wide drain poly-Si FinTFT developed in this paper exhibits excellent gate controllability and good high-frequency characteristics as compared with the conventional poly-Si TFT. The effect of the extended length of wide drain on the high-frequency characteristics of poly-Si FinTFT is investigated and analyzed by using the extracted small-signal parameters. Increasing the extended length not only can improve the high-frequency performance which degrade due to additional fringing capacitance in 3-D multigate structure but also can increase the breakdown voltage. This result suggest the possible use of the poly-Si TFT technology for RF integrated circuits and show a great potential to the future system on panel or system on glass.

The GIDL Current Characteristics of P-Type Poly-Si TFT Aged by Off-State Stress

The GIDL Current Characteristics of P-Type Poly-Si TFT Aged by Off-State Stress

Solution-derived SiO2 gate insulator formed by CO2 laser annealing for polycrystalline silicon thin-film transistors

The formation of perhydropolysilazane (PHPS)-based SiO2 films by CO2 laser annealing is proposed. Irradiation with a CO2 laser with optimum fluence transformed a prebaked PHPS film into a SiO2 film with uniform composition in the thickness direction. Polycrystalline silicon thin-film transistors (poly-Si TFTs) with a SiO2 film as the gate insulator were fabricated. When the SiO2 film was formed by CO2 laser annealing (CO2LA) at the optimum fluence of 20 mJ/cm2, the film had fewer OH groups which was one-twentieth that of the furnace annealed PHPS film and one-hundredth that of the SiO2 film deposited by plasma-enhanced chemical vapor deposition (PECVD) using tetraethyl orthosilicate (TEOS). The resulting TFTs using PHPS showed a clear transistor operation with a field-effect mobility of 37.9 ± 1.2 cm2 V−1 s−1, a threshold voltage of 9.8 ± 0.2 V, and a subthreshold swing of 0.76 ± 0.02 V/decade. The characteristics of such TFTs were as good as those of a poly-Si TFT with a SiO2 gate insulator prepared by PECVD using TEOS.

Microsecond Crystallization of Amorphous Silicon Films on Glass Substrates by Joule Heating

Joule-heating-induced crystallization (JIC) of amorphous silicon (a-Si) films was conducted by applying an electric pulse to a conductive layer located beneath or above the films. Crystallization occurs across the whole substrate surface within few tens of microseconds. The phase-transformation phenomena during the JIC process were detected electrically and optically by the in-situ measurements of input voltage/current and normal reflectance at wavelength of 532 nm. We devised a method for the crystallization of a-Si films while preventing arc generation; this method consisted of pre-patterning an a-Si active layer into islands and then depositing a gate oxide and gate electrode. Electric pulsing was then applied to the gate electrode formed using a Mo layer. JIC-processed poly-Si thin-film transistors were fabricated successfully, and the proposed method was found to be compatible with the standard processing of coplanar top-gate poly-Si TFTs. The p-channel JIC poly-Si TFT with W/L = 7 μm/7 μm exhibited a field effect mobility of 38.9 cm2/V-s, a threshold voltage of −2.8 V, and a gate voltage swing of 0.35 V/dec.

Poly‐Si TFTs with bottom‐gate structure using excimer laser crystallisation for AMOLED displays

An n-type polycrystalline silicon thin-film transistor (poly-Si TFT) with a bottom-gate structure using excimer laser annealing (ELA) for active matrix organic light-emitting diode displays is proposed. A problem with bottom-gate poly-Si TFTs (BGPs) using ELA, namely, the disconnection of poly-Si at the boundary of the gate metal during the ELA crystallisation, was solved by developing a novel process to control the slope of the gate metal. We realised ELA BGPs with pure-Mo gate having a thickness of more than 150 nm. The BGPs have better breakdown voltage characteristics compared with the conventional top-gate poly-Si TFTs because of its flat channel region and homogeneous electric field distribution in the gate insulator.

Deep Analysis of the Geometric Component in Charge Pumping of Polycrystalline Silicon Thin-Film Transistors

In this paper, we model the geometric component in a charge pumping (CP) technique of polycrystalline silicon thin-film transistors (poly-Si TFTs). This model is based on both remaining carrier types when the device transits from accumulation to inversion and vice versa. Therefore, it depends on gate length ( $L$ ) and width ( $W$ ) as well as on gate signal rise ( $t_{\!f}$ ) and fall time ( $t_{\!f}$ ). The proposed model shows good agreement with the experimental data. We have shown that the geometric component due to the remaining carriers, when poly-Si TFT transits from inversion to accumulation, is very small compared with that due to the transition from accumulation to inversion. Consequently, a new analytic CP model, depending on gate width, is developed for n-channel poly-Si TFT.

High-Performance Poly-Si Thin-Film Transistor With High-&lt;inline-formula&gt; &lt;tex-math notation="LaTeX"&gt;$k$ &lt;/tex-math&gt;&lt;/inline-formula&gt; ZrTiO&lt;sub&gt;4&lt;/sub&gt; Gate Dielectric

High-performance poly-Si thin-film transistors (poly-Si TFTs) with metal-induced laterally crystallized (MILC) poly-Si channel and high-k ZrTiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">4</sub> (ZTO) gate dielectric are shown for the first time. The MILC poly-Si and ZTO dielectric showed smooth interface (~1.8 nm) with a low interfacial layer and 4.1 nm of effective-oxide thickness. The electrical performance of MILC poly-Si TFT with ZTO exhibited low threshold voltage of -0.5 V, steep subthreshold slope of 0.25 V/decade, high I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</sub> /I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">OFF</sub> of 1.8 × 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">7</sup> , and high field-effect mobility of 250 cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> /Vs. These characteristics correspond to the best performance of the poly-Si TFTs with high-k gate dielectric reported so far. Moreover, the driving current and field-effect mobility of poly-Si TFT with ZTO gate dielectric were ten times higher than that of poly-Si TFT with deposited-SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> gate dielectric.

Effects of Channel Width on High-Frequency Characteristics of Trigate Poly-Si Thin-Film Transistors Fabricated by Microwave Annealing

In this paper, the high-frequency performance of trigate polycrystalline silicon thin-film transistors (poly-Si TFTs) is analyzed using low-temperature microwave annealing. The variation of the cutoff frequency and the maximum oscillation frequency with the width of the channel wire is investigated. A poly-Si TFT with a short channel and a narrow channel wire, annealed using microwave, has a high driving current, a good gate controllability, and a better high-frequency performance than one that annealed by rapid thermal annealing.

High-performance poly-Si TFT with ultra-thin channel film and gate oxide for low-power application

In this paper, an ultra-thin-body thin-film transistor (UTB-TFT) with a raised source/drain structure is demonstrated and compared with a conventional thin-film transistor. A significant suppression of leakage current and an improvement in subthreshold swing (SS) resulting from the reduced body thickness is observed. The minimum current can be decreased from 245 pA to 42 pA as the channel film thickness is scaled down from 60 nm to 10 nm. However, an ultra-thin-channel film constrains the average grain size and severely impacts the saturation current. Fortunately, by decreasing the gate oxide thickness from 20 nm to 10 nm, the saturation current of a UTB-TFT can be significantly increased from 13 μA to 25 μA. Experimental results suggest that UTB-TFTs with a sub-10 nm gate oxide display great promise for future low-power, high-performance three-dimensional integrated circuits.