poly-Si TFT Research Articles

Fabrication and characterization of low temperature polycrystalline silicon thin film transistors by ink-jet printed nickel-mediated lateral crystallization

High-performance polycrystalline silicon thin film transistors (poly-Si TFTs) were fabricated by using ink-jet printed nickel on large area glass substrates. Direct-printed Ni dots were used as a catalyst to crystallize the amorphous silicon into poly-Si for use in the channel region of TFT devices by metal-induced lateral crystallization. The fabricated poly-Si TFTs showed high field-effect mobility and on-off ratio that are comparable to the TFTs prepared using conventional semiconductor processes. The method presented here is a combination of bottom-up and top-down approaches and has a potential to be used in next generation high-performance poly-Si TFT fabrication.

Poly-Si Thin-Film Transistor Nonvolatile Memory Using Ge Nanocrystals as a Charge Trapping Layer Deposited by the Low-Pressure Chemical Vapor Deposition

We have successfully developed and fabricated a poly-Si thin-film transistor (poly-Si TFT) nonvolatile memory using Ge nanocrystals (Ge-NCs) as a charge trapping layer. Process compatibility and memory operation of the device were investigated. The Ge-NC trapping layer was directly deposited by low-pressure chemical vapor deposition at 370degC. Results show that the new poly-Si TFT nonvolatile Ge-NC memory has good programming/erasing efficiency, long charge retention time, and good endurance characteristics. These results show that poly-Si TFT nonvolatile Ge-NC memory is the promising nonvolatile memory candidate for system-on-panel application in the future.

High-Performance Poly-Silicon TFTs Using a High-$k$ $\hbox{PrTiO}_{3}$ Gate Dielectric

In this letter, a polycrystalline-silicon thin-film transistor (poly-Si TFT) with a high- <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">k</i> PrTiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> gate dielectric is proposed for the first time. Compared to TFTs with a Pr <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> gate dielectric, the electrical characteristics of poly-Si TFTs with a PrTiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> gate dielectric can be significantly improved, such as lower threshold voltage, smaller subthreshold swing, higher <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">I</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</sub> / <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">I</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">off</sub> current ratio, and larger field-effect mobility, even without any hydrogenation treatment. These improvements can be attributed to the high gate capacitance density and low grain-boundary trap state. All of these results suggest that the poly-Si TFT with a high- <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">k</i> PrTiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> gate dielectric is a good candidate for high-speed and low-power display driving circuit applications in flat-panel displays.

A Center-Offset Polycrystalline-Silicon Thin-Film Transistor With ${\rm n}^{+}$ Amorphous-Silicon Contacts

We have studied a bottom-gate polycrystalline-silicon thin-film transistor (poly-Si TFT) with amorphous-silicon (a-Si) n <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> contacts and center-offset gated structure, where intrinsic poly-Si is used in the center-offset region. The fabrication process is compatible with the conventional a-Si TFT with addition of thermal annealing for crystallization of a-Si. The bottom-gate poly-Si TFT with a 5-mum offset length exhibited a field-effect mobility of 18.3 cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> /V middots and minimum OFF-state current of 2.79 times 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-12</sup> A/mum at V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ds</sub> = 5 V. The leakage currents are two orders of magnitude lower than those of a nonoffset TFT with mobility drop from 23.8 to 18.3 cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> / Vmiddots.

EFFECT OF TRAP STATES AT THE OXIDE-SILICON INTERFACE IN POLYCRYSTALLINE SILICON THIN-FILM TRANSISTORS

This work presents the study of the effect of trap states at the oxide-silicon interface in lightly doped polycrystalline silicon thin-film transistors with large grains. In this study, it is assumed that the oxide-silicon interface traps are evenly distributed throughout the interface region and single grain boundary is present in the channel of poly-Si TFT. It is shown that improved device characteristics can be obtained by reducing the gate oxide thickness. It is also observed that as gate oxide thickness decreases for a constant value of trap state density in the oxide-silicon interface, the gate voltage required for channel formation is lowered and leads to a decrease in threshold voltage of the device. Calculated and experimental results are also found to be well consistent with each other.

Self-Heating Effect Induced NBTI Degradation in Poly-Si TFTs under Dynamic Stress

In this work, the characteristics of a p-type polysilicon thin-film transistor (poly-Si TFT) with dynamic bias stress were investigated. The ac stress is operated with the constant drain voltage and the varying gate voltage (0 to ) to degrade the devices. There are some phenomena which cannot be completely explained by the typical negative bias temperature instability (NBTI) mechanism in the experiment. In addition to NBTI, we suggest that the self-heating effect might be involved, because the self-heating effect could raise the channel temperature and cause the dissociation of the Si–H bonds at the poly- interface due to Joule heating. The released hydrogen reacts with and causes the fixed charge in the gate oxide. Thus, the degradation of the electrical characteristics of device is mainly dominated by the self-heating-induced NBTI effect.

Improvement of Electrical Characteristics in SPC-Si TFT Employing H2 Plasma Treatment

We fabricated PMOS SPC-Si TFTs which exhibit better uniformity than ELA poly-Si TFTs, and superior electrical stability compare to a-Si:H TFTs. We applied various H2 plasma treatments on solid phase crystallized silicon (SPC-Si) active layer prior to SiO2 gate insulator deposition, in order to improve the interface of SPC-Si. When the H2 plasma treatment with 100W power of PE-CVD was applied in the SPC-Si for 5 minutes, the electrical characteristics of the fabricated SPC-Si TFT was improved. It showed VTH of -3.91V, field effect mobility of 22.68cm2/Vs and subthreshold swing of 0.64 while the VTH of the other SPC-Si TFT was larger than -5V. We also showed that the stability of SPC-Si TFT was better than that of both poly-Si TFT and a-Si:H TFT.

Enhanced Drain Current Ripple Variation with Vertical and Horizontal Electrical Fields under Optical Illumination

A continuous-wave (CW) laser-crystallized (CLC) single-grainlike polycrystalline silicon (polysilicon) thin-film transistor (poly-Si TFT) also represents the similar electric characteristics with the mentioned device. Recently, poly-Si n-TFTs had been researched and successfully fabricated by C. Chen's team [1]. This TFT device demonstrates the excellent electron mobility, up to 530 cm2/V-s greater than that with low-temperature poly-silicon (LTPS) fabrication technology. In general, the TFT device is directly exposed by light from backside light source and outside light source beyond the display screen. Using some illuminants shining on the CLC poly-Si TFT, such as light emitting diode (LED), the current-voltage (I-V) characteristic of the TFT shows a current-ripple phenomenon. These interesting ripples actually may be magnified by the supplied drain and gate voltages. In this work, the red color LED was employed and the supplied drain and gate voltages were 0 ~ 7 V and 1 ~ 5 V, respectively.

Back- and Front-Interface Trap Densities Evaluation and Stress Effect of Poly-Si TFT

The polycrystalline silicon (poly-Si) TFT has two insulator interfaces between the polycrystalline silicon and front and back insulators. These interfaces have trap states, which affect the characteristics of poly-Si TFT. In the silicon-on-insulator (SOI) technology area, using the dual-gated, fully-depleted SOI MOSFET under the depleted back-channel condition, the back-interface trap density can be calculated through the front-channel threshold voltage and film thicknesses. The front-interface trap density is also evaluated changing the roles of both gates. This evaluation method for front- and back-interface trap densities is called the threshold-voltage method. To apply this threshold-voltage method to the “medium-thickness” poly-Si TFT, of which the channel is not fully depleted in normal single gate bias operation, the biases for both front and back gates are controlled to realize full depletion. Under the fully-depleted condition, the front- or back-threshold voltage of poly-Si TFT is carefully extracted by the second-derivative method changing back- and front-gate biases. We evaluated the front- and back-interface trap densities not only for normal operation but also under stress. To evaluate the bias and temperature stress effect, we used two types of samples, which are made by different processes. The evaluated front- and back-interface trap densities for both samples in initial state are around 5×1011 to 1.3×1012cm-2eV-1, which are almost the same as the reported values. Applying bias and temperature stress shows the variation of these interface-trap densities. Samples with large shifts of the front-channel threshold voltage show large trap density variation. On the other hand, samples with small threshold voltage shifts show small trap density variation. The variation of the back-interface trap density during the stress application showed a correlation to the front-channel threshold voltage shift.

A High-Performance Polysilicon Thin-Film Transistor Built on a Trenched Body

In this paper, a high-performance polysilicon thin-film transistor (poly-Si TFT) with a trenched body is proposed, fabricated, and studied. This new trenched TFT can be easily produced by filling and etch-back technology without destroying the channel film quality. The addition of the body trench is found to reduce the off-state leakage current by 70% on average, because the trench induces a carrier scattering effect in the poly-Si grain-boundary traps, thereby affecting the leakage path. Although the off-state current is substantially reduced, the on-state current is comparable with that of a conventional TFT. Our multiple-trenched-body TFT is also shown to improve the breakdown voltage by 11%.

Dynamic Characteristics of Multi-Channel Metal-Induced Unilaterally Precrystallized Polycrystalline Silicon Thin-FilmTransistor Devices and Circuits

Electrical properties of multi-channel metal-induced unilaterally precrystallized polycrystalline silicon thin-film transistor (MIUP poly-Si TFT) devices and circuits were investigated. Although their structure was integrated into small area, reducing annealing process time for fuller crystallization than that of conventional crystal filtered MIUP poly-Si TFTs, the multi-channel MIUP poly-Si TFTs showed the effect of crystal filtering. The multi-channel MIUP poly-Si TFTs showed a higher carrier mobility of more than 1.5 times that of the conventional MIUP poly-Si TFTs. Moreover, PMOS inverters consisting of the multi-channel MIUP poly-Si TFTs showed high dynamic performance compared with inverters consisting of the conventional MIUP poly-Si TFTs.

Characterization of poly-Si TFT variation using interdigitated method

In this paper, the device variation characteristic of poly-Si TFTs is statistically investigated. First the variation of devices is examined with respect to different device distance. It is found that the device variation would exhibit similar behavior for different device distance. Then, in order to study the method to suppress device variation, the interdigitated layout is adopted. It is found that though the variation behavior of the poly-Si TFTs is much more serious and complicated than MOSFETs, the law of area can still be utilized to describe the variation behavior in the interdigitated layout. The fitting parameters in law of area can provide insights for understanding the intrinsic variation behavior for poly-Si TFTs and the discussion about the variation for the device with various channel width is provided. The variation behavior of poly-Si TFTs is then compared with amorphous silicon TFTs and single crystal silicon MOSFETs. The impacts of poly-Si TFT variation on circuit design and performance is also discussed.

Characterizing Fluorine-Ion Implant Effects on Poly-Si Thin-Film Transistors With ${\hbox{Pr}}_{2}{\hbox{O}}_{3}$ Gate Dielectric

The fluorine ion implantation applied to the polycrystalline silicon thin-film transistors (poly-Si TFTs) with high-k Pr2O3 as gate dielectric is investigated for the first time. Using the Pr2O3 gate dielectric can obtain a high gate capacitance density and thin equivalent-oxide thickness, exhibiting a greatly enhancement in the driving capability of TFT device. Introducing fluorine ions into the poly-Si film by fluorine ion implantation technique can effectively passivate the trap states in the poly-Si film and at the Pr2O3/poly-Si interface to improve the device electrical properties. The Pr2O3 TFTs fabricated on fluorine-implanted poly-Si film exhibit significantly improved electrical performances, including lower threshold voltage, steeper subthreshold swing, higher field-effect mobility, lower off-state leakage current, and higher on/off current ratio, as compared with the control poly-Si Pr2O3 TFTs. Also, the incorporation of fluorine ions also improves the reliability of poly-Si Pr2O3 TFTs against hot-carrier stressing, which is attributed to the formation of stronger Si-F bonds. Furthermore, superior threshold-voltage rolloff characteristic is also demonstrated in the fluorine-implanted poly-Si Pr2O3 TFTs. Therefore, the proposed scheme is a promising technology for high-performance and high-reliability solid-phase crystallized poly-Si TFT.

Design of system-on-glass for poly-Si TFT OLEDs using mixed-signals simulation

AMOLEDs (active-matrix organic light emitting diodes) employing poly-Si TFT have been used to integrate peripheral circuits on a glass to reduce the cost through the use of dead space on the glass. The system-on-glass (SOG) development provides enormous challenges to the developers, usually verifying the SOG by transistor-level simulation. IR-drop modeling is needed to reduce the uniformity degradation in the OLED image quality. This paper presents a full panel simulation technique for OLED driver and pixels that is integrated on a glass using the mixed-signals circuit design and the proposed process shows excellent capabilities relating to the capacity and the speed.

Negative Data Insertion Method for Suppressing Hysteresis of Polysilicon Thin-Film Transistors

The electrical hysteresis of polysilicon thin-film transistors (poly-Si TFTs) employing a negative data insertion (NDI) has been investigated. It is known that the image sticking in active-matrix organic light emitting diode displays using the poly-Si TFT back plane was mainly caused by the hysteresis of driving TFT in a pixel. In this paper, we propose a type of NDI method using inverse data signals in order to suppress the hysteresis of poly-Si TFTs. Experimental results show that the NDI was very effective to reduce the hysteresis level of poly-Si TFTs induced by carrier trapping and detrapping.

Fabrication of Low Temperature Polycrystalline Silicon Thin-Film Transistor Nonvolatile Memory Devices for Digital Memory on Glass Applications

We fabricated the nano-floating gate memory (NFGM) devices on the polycrystalline silicon (poly-Si) films crystallized by excimer laser annealing (ELA) method for thin-film transistor liquid-crystal display (TFT-LCD) with a new integration technology called digital memory on glass (DMOG). The In2O3 nano-dots were formed in polyimide gate insulating layers at low temperature as the charge storages of nonvolatile memory for DMOG applications. The memory window of low temperature poly-Si TFT nonvolatile memory with In2O3 nano-dots embedded in polyimide was larger than 3.2 V and the memory characteristics were considerably improved by 3% hydrogen diluted N2 ambient annealing.

Variation and mismatch effects of the low-temperature poly-Si TFTs on the circuit for the X-ray active matrix sensor

The application of the capability of low-temperature poly-Si TFT circuits for high resolution X-ray active matrix sensor is explored. The integration of poly-Si TFT circuits on the glass enables an easy connection for the sensor array with fine pixel pitch. A novel charge sensitive amplifier circuit employing poly-Si TFTs is proposed for the readout system of the active matrix sensor. It can considerably increase the circuit’s immunity to the unavoidable threshold voltage variations of the poly-Si TFTs. The V TH mismatch effect of the TFTs, which results in the offset voltage of the charge amplifier, can also be suppressed by the proposed circuit. However, the noise arisen from the V TH mismatch can be even larger than that from the V TH variation after compensation. It reflects that, for higher bit digital X-ray image sensors, the mismatch effect of the devices must be properly taken into consideration.

High-Performance Poly-Si TFTs With $\hbox{Pr}_{2} \hbox{O}_{3}$ Gate Dielectric

In this letter, a polycrystalline silicon thin-film transistor (poly-Si TFT) with high-quality praseodymium oxide (Pr2O3) gate dielectric is proposed. Compared to TFTs with tetraethoxysilane gate dielectric, the electrical characteristics of poly-Si TFTs with Pr2O3 gate dielectric can be significantly improved, such as lower threshold voltage, lower subthreshold swing, triple ON/OFF current ratio, and a field-effect mobility that is about twice higher, even without any hydrogenation treatment. These improvements can be attributed to the high gate capacitance density by using a high-kappa gate dielectric. Therefore, the poly-Si TFT with Pr2O3 high-kappa gate dielectric is a promising candidate for high-speed and low-power display driving circuit applications in flat-panel displays.

Hysteresis Phenomenon in Sequential Lateral Solidification poly-Si Thin Film Transistor at low temperature (213K)

ABSTRACTWe have investigated temperature dependence on the hysteresis phenomenon of SLS poly-Si TFT on a glass substrate, extremely at low temperature (213K). The p-type sequential lataral solidification (SLS) polycrystalline Silicon (poly-Si) TFT was fabricated on glass substrate. As the temperature was reduced, it was observed that hysteresis phenomenon was increased, whereas the hysteresis was suppressed at high temperature. This could be explained by a difference of initially electron and hole trapped charges into gate insulator is much larger in low temperature than in high temperature. And we have verified that drain current was changed with a different previous gate starting voltage even at same bias condition by experimental results due to the hysteresis phenomenon of SLS poly-Si TFT. Hysteresis of SLS poly-Si TFT should be improved for a pixel element of high quality AMOLED display.

Suppression of TFT leakage current effect on active matrix displays by employing a new circular switch

We have proposed a new poly-Si TFT pixel, which can suppress TFT leakage current effect on active matrix organic diode (AMOLED) displays, by employing a new circular switching TFT and additional signal line for compensating the leakage current. When the leakage current of switching TFT is increased, the V GS of the current driving TFT in the proposed pixel is not altered by the variable data voltages due to the circular switching TFT. Our simulation results show that OLED current variation of the proposed pixel can be suppressed less than 3%, while that of conventional pixel exceeds 30%. The proposed pixel may be suitable to suppress the leakage current effect on AMOLED display.