Gate Bias Polarity Research Articles

Formation of oxide-trapped charges in 6HSiC MOS structures

Gamma-ray irradiation effects on MOS structures formed on the silicon and the carbon faces of 6HSiC are examined by using high frequency capacitance-voltage method. The accumulation of radiation-induced trapped charges in the oxide near the interface depends on not only the gate bias polarity during irradiation but also the face type of 6HSiC. The fomation mechanisms of the trapped charges are discussed in conjunction with the face type and the bias polarity.

Investigation of stress induced leakage current in CMOS structures with ultra-thin gate dielectrics

Investigation on the stress induced leakage current shows that the SILC degradation rate follows a pure power law with the injection dose which is almost independent of gate bias polarity and stress current intensity. Moreover, it has also been found that the SILC is invariant with the device area, substrate type but could depend on the gate material in the case of P+ polysilicon due to boron-induced defects in the bulk of the oxide.

Post-Stress Interface-Trap Generation in P-Channel Metal-Oxide-Semicondutor Field-Effect-Transistors after Hot-Electron Stress

Post-stress electron discharging and interface trap generation in p-channel Metal Oxide Semiconductor Field-Effect-Transistors (MOSFETs) after drain avalanche hot-electron stress (DAHE) are investigated. It was found that the effect of electron discharging must be taken into account for the interpretation of charge-pumping characteristics after DAHE stress. To clarify the physical mechanism underlying post-stress interface trap generation, the effect of hot-electron injection and post-stress gate bias are studied. electron discharging and post-stress interface trap generation are strongly dependent on the gate bias polarity and magnitude. A physical model is proposed which is based on mechanisms involving carrier injection, recombination and the breaking of Si–H bonds at the Si/SiO2 interface.

Polarity dependence of charge to breakdown and interface state generation of oxynitride gate dielectrics prepared by rapid thermal processing

MOS devices were fabricated with dry thermal oxides, nitrided oxides and annealed nitrided oxides. The anneals were performed in O2 or N2 ambients using rapid thermal processing. Charge to breakdown, Qbd, and interface state generation, ΔDit for these devices were studied using Fowler–Nordheim electron injection. The gate bias polarity dependence of Qbd and ΔDit was investigated. A model is proposed to explain the observed dependence of these quantities on the polarity of injection and process parameters.

A new approach to study electron and hole charge separation at the semiconductor-insulator interface

The charge transport and trapping properties of insulating films on semiconductors are related to reliability problems in MOSFETs and memory properties of nonvolatile memory devices. Physically based device models require delineation of electron and hole processes. Until recently, electron and hole charge separation at the semiconductor-insulator interface had been restricted to one gate bias polarity because of minority-carrier recombination-generation at the silicon surface. It is shown that a dual-channel transistor accomplishes electron and hole charge separation on the same microstructure for both gate polarities, obviating the need for complementary transistors and assumptions of identical dielectric and interface properties for a transistor pair. This approach is applied to the study of scaled dielectric oxide-nitride-oxide (ONO) memory devices, and their charge trapping characteristics are discussed. >

Gate bias polarity dependence of charge trapping and time-dependent dielectric breakdown in nitrided and reoxidized nitrided oxides

The gate bias polarity dependence of charge trapping and time-dependent dielectric breakdown (TDDB) in nitrided and reoxidized nitrided silicon dioxides prepared by rapid thermal processing (RTP) is reported. Charge trapping during high-field injection can be reduced by rapid thermal nitridation for both substrate and gate injection. While reoxidation of nitrided oxides shows further reduction in charge trapping for substrate injection, degradation is observed for gate injection. Similar effects are observed for TDDB: reoxidized nitrided oxides show charge-to-breakdown in excess of 300 C/cm/sup 2/ for substrate injection, but less than 30 C/cm/sup 2/ for gate injection. These effects are related to the nitrogen and hydrogen profiles in the oxides. By tailoring the process conditions, a symmetric behavior of NO and RONO films with low charge trappings and Q/sub BD/ in excess of 50 C/cm/sup 2/ is possible, making them attractive as long-lifetime dielectrics from EEPROM (electrically erasable programmable ROM) and flash EEPROM technologies.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Time-dependent evolution of interface traps in hot-electron damaged metal/SiO2/Si capacitors

The interface traps in metal/SiO 2 /Si (MOS) capacitors generated by Fowler-Nordheim electron injection change with time after injection. Immediately after injection, a peak of the interface trap distribution appears above the midgap energy ( \simE_{v} + 0.75 eV) in all of the samples studied. This peak, along with its background, increases or decreases with time at room temperature, depending on the gate bias polarity during injection, the initial damage level, the gate-induced stress, and the presence of certain chemical impurities in the gate oxide. In the cases when this peak decreases with time, a second peak below midgap ( \simE_{v} + 0.35 eV) develops, and this peak grows with time at the expense of the first peak. The important factors that affect the time-dependent behavior of the interface traps are discussed.

Degradation of metal/oxide/semiconductor structures by Fowler-Nordheim tunnelling injection

The behaviour of thin metal/oxide/semiconductor (MOS) structures with polycrystalline silicon (poly-Si) or silicon aluminium gates subjected to stresses caused by Fowler-Nordheim tunnelling injection was analysed. Native electron capture centres in the bulk SiO 2 were characterized by their capture cross-section, their density and their centroid localization in the oxide layer by means of capacitance and conductance measurements. The trapping was independent of the gate bias polarity during injection. The other aging mechanism is interface (SiO 2-Si and gate-SiO 2) degradation owing to the generation of new centres in the oxide. The new electrically active sites acting as stable electron traps were analysed in correlation with the technological process parameters such as oxidation ambient environment (dry or wet, with or without HCl) and gate type (aluminium or poly-Si). Our results seem to be consistent with the hypothesis that aging of MOS structures under electrical injection is essentially controlled by interfacial phenomena involving the formation of intrinsic defects at the Si-SiO 2 interface. It appears that poly-Si gate structures are the least sensitive to intense Fowler-Nordheim injection stresses.

Interface-trap generation modeling of Fowler–Nordheim tunnel injection into ultrathin gate oxide

Two mechanisms for interface-trap generation during Fowler–Nordheim tunnel injection into gate oxide are confirmed by the results of experiments with changes in the interface-trap density for positive and negative gate bias injections. One mechanism is independent of gate bias polarity during injection, the other mechanism is present only in negative gate bias injection. Agreements between the measured and calculated generation cross sections for both mechanisms indicate that: (i) The first mechanism is quantitatively explained using a broken-bond model by taking account of electron heating due to an oxide field during passage through the oxide conduction band. (ii) The second mechanism is quantitatively explained using a heated electron impact model where electrons heated by the oxide field generate interface traps by directly breaking the interface weak bonds when electrons cross the interface between the SiO2 and the Si substrate.