PMOS Pair Research Articles

X-Band CMOS Rectifier With 4% Efficiency at −35 dBm for Wireless Power Transmission

This paper proposes a radio frequency (RF) rectifier topology for low-power wireless power transmission (WPT) applications in the X band. The rectifier consists of a biased PMOS pair and is matched to the RF signal source impedance using a PCB transmission line (TL) matching network. It is demonstrated that a clever optimization of the bias voltage enables the rectifier to achieve greater sensitivity and efficiency than previous works at X band. The rectifier was designed in a 45 nm silicon-on-insulator (SOI) process and operates at a frequency of 9.64 GHz. It achieves a power conversion efficiency (PCE) of 4% and 46% at power levels of −35 dBm and −10 dBm, respectively.

A 250 MS/s 65.8-dB SNDR SAR ADC With Cross-Phase Common-Mode Feedback and Reconfigurable Inverter-Based Preamplifier in 28-nm CMOS

This brief presents a 250 MS/s 12b successive-approximation-register (SAR) analog-to-digital converter (ADC) in 28 nm CMOS. The inverter-based preamplifier is introduced to suppress comparator noise. To improve the ADC robustness and speed, first, a cross-phase common mode feedback which explores the common mode voltage during the sampling phase, is proposed to address the PVT and input common mode voltage sensitivity of the inverter-based preamplifier. Second, a reconfigurable method is proposed to eliminate the long recovery time of the preamplifier at large input signals, as well as reduce the kickback noise at small input signals. Third, a PMOS pair with deliberate timing is introduced to accelerate the comparator regeneration without deteriorating its noise. The ADC employs 360 fF/side sampling capacitance and takes 2 ns conversion time to resolve 15 raw bits. Fabricated in 28 nm CMOS, the prototype ADC achieves 65.8 dB SNDR and 80.9 dB SFDR for a near-Nyquist input, occupies an active area of 0.01 mm2 and consumes a power of 4.7 mW, resulting in a Walden FOMW of 11.8 fJ/conv-step and a Schreier <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${\mathrm {FOM}}_{{\boldsymbol{S}}}$ </tex-math></inline-formula> of 170.0 dB, respectively. Last but not least, the ADC attains a rail-to-rail input CM range.

Power‐efficient voltage up level shifter with low power–delay product

SummaryIn this article, a power‐efficient hybrid voltage up level shifter (LS) is designed. By using a combination of a current mirror (CM) and a cross‐coupled pMOS pair in a pull‐up circuitry, the dynamic power is reduced significantly even at boosted switching speed. The designed LS circuit, which occupies a small silicon area, consists of 10 transistors and is mainly suitable for ultra‐low‐power applications, such as wireless sensor nodes and biomedical appliances. Moreover, it can convert extreme low‐level input voltages to the high supply voltage levels. The results obtained from post‐layout simulations in a standard 180‐nm CMOS process illustrate that the designed LS circuit has total power consumption, static power dissipation, and propagation delay of 33.93 nW, 253 pW, and 9.09 ns, respectively, at 1 MHz with a minimum supply voltage (VDDL) of 0.4 V and nominal supply voltage (VDDH) of 1.8 V. Also, the designed LS can convert an input voltage of 0.12–1.8 V at 10 kHz.

A 67.4–71.2-GHz nMOS-Only Complementary VCO With Buffer-Reused Feedback Technique

In this letter, a mm-wave nMOS-only complementary voltage-controlled oscillator (VCO) is proposed. By replacing the large-sized cross-coupled pMOS pair in the classical complementary VCO structure with smaller and faster nMOS pair employing buffer-reused feedback technique, the parasitic capacitance introduced by the pMOS pair is reduced and the resonant frequency is thus effectively increased. Meanwhile, the negative resistance compensation is enhanced by the feedback reused buffer and the power efficiency is thus improved. The VCO, implemented in 45-nm CMOS SOI technology, occupies an area of 0.038 mm2 including the buffer and is tunable from 67.4 to 71.2 GHz. The optimum phase noise measured at 69.4 GHz is −94.4 dBc/Hz at 1-MHz offset. The VCO and buffer consume 4.5 mW from a 1-V supply.

A $6.5\times7\,\mu$ m2 0.98-to-1.5 mW Nonself-Oscillation-Mode Frequency Divider-by-2 Achieving a Single-Band Untuned Locking Range of 166.6% (4–44 GHz)

The common self-oscillation-mode (SOM) frequency dividers have a high- $Q$ sensitivity curve limiting the locking range (LR). This letter reports a non-SOM (NSOM) frequency divider-by-2. Fabricated in 65-nm CMOS, it occupies a die area of $6.5\,\,\times 7\,\,\mu \text{m}^{2}$ , and measures a single-band untuned LR of 166.6% (4–44 GHz), over a small input range $ . The key technique is a load-modulated dynamic latch aided by a current-reuse cross-coupled pMOS pair. The achieved figure-of-merit of 26.6 GHz/mW compares favorably with the state-of-the-art.

Design of current mirror integration ROIC for snapshot mode operation

Current mirror integration (CMI) read out integrated circuit (ROIC) topology provides a low input impedance to photo-detectors and provides large injection efficiency, large charge handling capacity and snapshot mode operation without in-pixel opamps. The ROIC described in this paper has been implemented with a modified current mirror circuit, with matched PMOS pairs for detector input stage and its biasing. The readout circuit has been designed for 30 × 30 μm2 pixel size, 4 × 4 array size, variable frame rate, 5 Mega pixel per second (Mpps). Experimental performance of the test chip has achieved 15 Me charge handling capacity, a high dynamic range of 83 dB, 99.8% linearity and 99.96% injection efficiency. The ROIC design has been fabricated in 3.3 V 1P6M UMC 180 nm CMOS process and tested up to 5 MHz pixel rate at room and at cryogenic temperature.

An Ultra Low Voltage Low Power Self Biased Latched Comparator with Wide Input Common Mode Range for Biomedical Applications

This work describes an ultra low voltage, low power and self biased comparator with wide input common-mode range. The proposed comparator consists of a preamplifier followed by a regenerative back-to-back inverter latch, where two push pull NMOS and PMOS pairs are exploited to bias the preamplifier and adjust its output common mode voltage. This leads to a wide input common mode voltage range (from 0 V to 390 mV). Furthermore, the operation of proposed structure is relatively insensitive to process and temperature variations due to the push pull transistors, and low power consumption is achieved through sub-threshold region operation. The comparator circuit is designed using 65-nm CMOS technology with minimum supply voltage of 0.4 V. Simulation results show an average power consumption ranging from 141 nW to 188 nW for different input common mode voltage levels, where a simple power gating technique is employed to further reduce the power consumption. The Monte Carlo simulation shows an average offset of 450 μV with standard deviation of 3.3 mV. In addition, the comparator shows a kickback noise range of 0.3–2.4 mV (with input common mode range from 0 V to 390 mV) and input referred noise of 0.9 mV. The proposed comparator operates up to clock frequency of 1 MHz in most process corners and temperature range of 0–100°C which is suitable for most of the biomedical sensing applications.

Low Voltage Low Power Quadrature LC Oscillator Based on Back-gate Superharmonic Capacitive Coupling

This work introduces a new low voltage low power superharmonic capacitive coupling quadrature LC oscillator (QLCO) made by coupling two identical cross-connected LC oscillators without tail transistor. In each of the core oscillators, the back-gate nodes of the cross-coupled NMOS pair and PMOS pair, acting as common mode nodes, have been connected directly. Then the core oscillators are coupled together via capacitive coupling of the PMOS common mode node in one of the core oscillators to the NMOS common mode node in the other core oscillator, and vice versa. Only capacitors are used for coupling of the two core oscillators and therefore no extra noise sources are imposed on the circuit. Operation of the proposed QLCO was investigated with simulation using a commercial 0.18 µm RF CMOS technology: it shows a power dissipation of 5.2 mW from a 0.6 V supply voltage. Since the proposed core oscillator has Complementary NMOS and PMOS cross coupled pairs, and capacitive coupling method will not introduce extra phase noise, so this circuit can operate with a low phase noise as low as −126.8 dBc/Hz at 1 MHz offset from center oscillation frequency of 2.4 GHz, as confirmed with simulation.

Charge-mixer based on MOS interface-trap charge pump

A 3.3 V charge-mixer device in a 0.35 µm CMOS process detects the intensity and phase of a modulated signal. A two PMOS pair is used as charge-mixer to exploit the interface-trap charge pump phenomenon. Using clocking between accumulation and inversion, the two transistors perform a voltage-to-charge conversion of the input signal and transfer this charge to the two outputs synchronously to the applied signal.