PMOS Capacitors Research Articles

Characterization of SiC/SiO<sub>2</sub> Interface State under Different NO Annealing

Interface properties of 4H-SiC N-MOS and P-MOS capacitors with two different NO annealing conditions are characterized by the conductance method. With the enhancement of nitrogen passivation, the density of interface states is reduced as expected. Fast interface states (response frequencies >1 MHz) are observed for both N-MOS and P-MOS capacitors with weak NO passivation. After strong NO passivation, the fast states are passivated to the interface states with lower response frequency in N-MOS and significantly suppressed in P-MOS. It indicates that the nitridation may passivate the defects by shifting them from shallow level to deep level.

Analysis of Bulk and Surface Radiation Damage in n+ in p SFz Si Micro Strip Detectors for the Future High Luminosity Collider Experiments: TCAD Simulation and Measurements

Within the framework of CERN RD50 collaboration, several radiation damage models for n/p-SFz, n-MCz Si have been explored for the better understanding of the experimental results in radiation damage analysis of the irradiated Si detectors. In the present paper, the important review on the microscopic radiation damage model for the p-type SFz Si detector combining the surface and radiation damage effects that can be used to simulate radiation damages effects in the heavily irradiated detectors for the good comparison of the experimental data and simulation result. The surface radiation damage models were extracted from the experimental measurements on the p-MOS capacitor and Gate-Controlled Diodes irradiated by Gamma or X-ray radiations in the range of 10 to 500 Mrad (Si). Whereas, the bulk damage model microscopic parameter was extracted from the experimental (TSC, DLTS) measurements on the n in p-SFz Si microstrip detector. The radiation damage (surface and bulk) models can be fed into the commercial Synopsys TCAD device simulator program for the designing and optimization of the detector, which can be used in the very harsh radiation environment of the HL-LHC, or FCC experiment. The objective of this analysis was to verify the experimental results using the new microscopic radiation damage models on the p-SFz Si for the radiation damage analysis of p- SFz Si detectors irradiated by proton, neutron or mixed at very high fluences. The results were verified by comparison of the experimental data with TCAD simulation.

Effect of high-radiation-dose-induced structural modifications of HfSiO4/n-Si on electrical characteristics

High-k/n-Si structures were formed with HfSiO4 films annealed at the temperature range of RT (room temperature)-900 °C and radiation-induced structural modifications were determined by XRD (X-ray diffraction) and XPS (X-ray photoelectron spectroscopy) techniques in the study. The effect of oxygen-deficient bond contents on the electrical characteristics of HfSiO4 pMOS (n type Metal Oxide Semiconductor) capacitors whose radiation response was investigated in the 0–50 kGy dose range was investigated. While no XRD peak was observed before and after irradiation at RT and 500 °C-HfSiO4/n-Si, crystallization started with irradiation at 900 °C. The dielectric constant of the film was found in the range of 16–23. It was determined that Hf–Hf oxygen-deficient bonds act as negative charge trapping centers, while Hf–Si and Si–Si oxygen-defective bonds act as positive charge trapping centers. The direction of the C–V (Capacitance-Voltage) curve changed continuously with increasing radiation dose. The change in the interface trap charge density was found to be higher than the change in the oxide trap charge density for all doses in RT-HfSiO4 pMOS capacitor and for 1 kGy at 500 °C-HfSiO4 pMOS capacitor. Oxygen defective bond content and Hf-O-Si/Si–O–Si ratios were sufficient to establish a link between structural analyses and electrical characteristics at some doses. In some cases, the frequency-dependent charges had a more dominant effect on the radiation response of the device compared to the oxide trap charges.

Novel Band-Edge Work Function Performance Modulation via NPT with PMOS1st/NMOS1st Laminated Stack for PMOS Low Power Target

In this paper, the band-edge work function performance is systematically investigated and modulated via novel nitrogen plasma treatment (NPT) with the advanced PMOS1st (TiN/TiN/TiAlC) and NMOS1st (TiN/TiN) laminated stacks for the fabricated PMOS capacitors. The basic multi-VT performance is strongly modulated by controlling NPT process. 1) Flatband voltage (VFB) shifts towards band edge are obtained as +120 mV (undiluted), +430 mV (diluted) for PMOS1st and +80 mV (undiluted), +210 mV (diluted) for NMOS1st. 2) By manipulating the NPT process from undiluted and diluted case, it can provide significant high band-edge effective work function ranging from 4.89 eV (undiluted) to 5.21 eV (diluted) for PMOS1st and 5.22 eV (undiluted) to 5.35 eV (diluted) for NMOS1st laminated stack, respectively. 3) NPT diluted with hydrogen is observed to maintain ultralow bulk trap density (1.11 × 1011 cm−2 for PMOS1st and nearly zero for NMOS1st) and interface trap density (3.34 × 1011 eV−1 cm−2 for PMOS1st and 6.45 × 1011 eV−1 cm−2 for NMOS1st). The significant band-edge work function modulation and very low bulk and interface trap density demonstrate the novel NPT with PMOS1st/NMOS1st laminated stack is very promising to achieve the target of PMOS low-power application in the further technology node.

Radiation response of zirconium silicate P-MOS capacitor

The chemical bonding of zirconium silicate films were examined by FTIR. The capacitance-voltage (C-V) measurements before and after irradiation were performed at high frequency. Furthermore, significant changes were observed depending on the radiation dose of the oxide traps and the intensity of the interface state. The sensitivity of this MOS capacitor is 4.3, 31.3 and 15.6 times less sensitive compared to the same thickness as Sm2O3, Al2O3 and Gd2O3. Therefore, it can be used as radiation-resistant material in nuclear reactors and space applications due to its stable electrical characteristics compared to other defined dielectrics. Interface states, (Nit) Barrier potential (Φb) and oxide traps (Not) have also been investigated depending on the radiation effects. Φb is one of these important electrical properties. Φb values decreased with increasing in radiation dose. Besides, radiation and frequency dependent dielectric constant (ε′), dielectric loss (ε″) and dielectric loss tangent (tanδ) and conductivity (σac) of zirconium silicate were investigated. It is concluded that high-k zirconium Silicate is suitable for electronics applications in radiation harsh environment.

Improvement of AM–PM in a 33-GHz CMOS SOI Power Amplifier Using pMOS Neutralization

This letter presents two highly efficient two-stage power amplifiers (PAs) for 5G applications, implemented in a 22-nm slilicon on insulator (SOI) CMOS technology. High efficiency is achieved by carefully designing the power cells and optimizing the layout. Capacitive neutralization is used to improve the stability and the gain. Both PAs are similar except for the use of nMOS neutralization capacitors in the first one. In the second PA, we propose the use of pMOS capacitors instead to enhance significantly both stability and AM–PM linearity at the same time. For both PAs, the saturated output power is 12.7 dBm and $\text{P}_{\mathrm {1\,dB}}$ is 11.9 dBm from a 0.9-V supply at 33 GHz with a power-added efficiency (PAE) at $\text{P}_{\mathrm {1\,dB}}$ of more than 36%. The PAE at $\text{P}_{\mathrm {sat}}$ is 38% and 40% for the PA with nMOS and pMOS neutralizations, respectively. The AM–PM up to $\text{P}_{\mathrm {3\,dB}}$ for the PA with nMOS neutralization is 7°, and for the one with pMOS neutralization, it is less than 1.3° thanks to the proposed technique.

Improvement of the electrical performance of Au/Ti/HfO2/Ge0.9Sn0.1 p-MOS capacitors by using interfacial layers

The impact of different interfacial layers (ILs) on the electrical performances of Au/Ti/HfO2/Ge0.9Sn0.1 metal oxide semiconductor (MOS) capacitors is studied. Parallel angle resolved x-ray photoelectron spectroscopy measurements show that germanium diffuses into the HfO2 layer when no IL is used. This results in an increase in the tin content at the interface and a high interface state density. We demonstrate that the use of an IL prevents germanium and HfO2 intermixing and improves the electrical performance of MOS capacitors. Several ILs are studied such as alumina (Al2O3) and plasma oxidized GeSn (GeSnOx) prior to HfO2 deposition. C–V measurements correlated with simulations made by a customized analytical model indicate an interface state density of 5 × 1011 eV−1 cm−2 for the HfO2/GeSnOx/Ge0.9Sn0.1 gate stack. This result is promising for the integration of high mobility GeSn channels in CMOS devices.

Impact of Wet Treatments on the Electrical Performance of Ge0.9Sn0.1-Based p-MOS Capacitors

We have investigated the impact of different wet treatments on the electrical performances of germanium–tin (GeSn)-based p-MOS capacitors with 10% Sn. Atomic force microscopy (AFM) showed the prese...

Improved channel mobility of 4H-SiC n-MOSFETs by ultrahigh-temperature gate oxidation with low-oxygen partial-pressure cooling

An n-channel metal–oxide–semiconductor field-effect transistor (MOSFET) with high field-effect mobility (μFE) on 4H-SiC (0001) was fabricated using an ultrahigh-temperature gate-oxidation technique, and its improved channel mobility was demonstrated by employing a low-oxygen partial-pressure cooling procedure. The ideal flatband voltage for n-MOS and p-MOS capacitors and hysteresis-free drain current–gate voltage (Id–Vg) characteristics were obtained through gate oxidation at 1450 °C in 100% O2 ambient at 1 atm followed by the low-oxygen partial-pressure (1%) rapid-cooling procedure. From the Id–Vg characteristics, a μFE of 15.8 cm2 V−1 s−1 was obtained under the pure O2 gate-oxidation process.

Impact of interfacial layer using ultra-thin SiO2 on electrical and structural characteristics of Gd2O3 MOS capacitor

The aim of present study is to improve the quality of Gd2O3/p-Si MOS structure by reducing interface trap charge density. Therefore, the ultra-thin SiO2 layer was grown to high-k/Si interface. The effect of the post deposition annealing on the structural properties of the Gd2O3/SiO2 films and electrical characteristics of the Al/Gd2O3/SiO2/p-Si/Al were investigated for three different temperature. Besides, the effect of the series resistance and measurement frequency on the electrical characteristics of the p-MOS capacitors was examined in detail. 118 nm-thick Gd2O3 films were grown by RF magnetron sputtering following the 5 nm-thick SiO2 deposition on p type Si wafer by dry oxidation method. While the Gd2O3 monoclinic characteristic peaks were observed in the Gd2O3/SiO2/Si structures annealed at 600 °C and 800 °C, the XRD spectra of as-deposited and annealed at 400 °C sample pointed out Gd silicate formation. –Si, –O, –Gd, and –H bonds were defined in the FTIR spectra of all samples. The frequency dependent capacitance–voltage (C–V) and conductance–voltage (G/ω–V) characteristics of Gd2O3/SiO2 MOS capacitor were measured. Strong accumulation capacitance values in these devices did not change significantly depending on frequency. Unlike from the MOS capacitor with as-deposited and annealed Gd2O3/SiO2 at 400 °C, the interface trap charge density $$({N_{it}})$$ increased with increasing voltage frequency for the samples annealed at 600 °C and 800 °C. No significant change in the border trap density $$({N_{bt}})$$ with increasing frequency was observed in the MOS capacitor except for as-deposited device. The barrier height $$({\Phi _B})$$ increased with increasing frequency for all Gd2O3/SiO2 MOS capacitors.

Investigating FinFET Sidewall Passivation Using Epitaxial (100)Ge and (110)Ge Metal–Oxide–Semiconductor Devices on AlAs/GaAs

Device-quality crystallographically oriented epitaxial (100)Ge and (110)Ge were grown on GaAs substrates using a large bandgap AlAs buffer. Electrical characteristics of p-type metal–oxide–semiconductor (pMOS) capacitors, fabricated from the aforementioned material stacks, are presented for the first time. High-resolution cross-sectional transmission electron microscopy analysis demonstrated atomically abrupt heterointerfaces between Al2O3/Ge as well as Ge/AlAs for both (100) and (110) orientations. Various process conditions were implemented during MOS capacitor fabrication to study their impact on the Al2O3/Ge interface. The fabricated pMOS devices demonstrated excellent electrical characteristics with efficient modulation of the Fermi level from midgap to the conduction band edge, corresponding to a minimum ${D}_{\text {it}}$ value of ${1.2} \times {10}^{11}$ cm $^{-2}\cdot $ ev−1 on (100)Ge, indicative of a high-quality oxide/Ge heterointerface, and an effective electrical passivation of the Ge surface. Postdeposition annealing under O2 was found to be less effective at reducing oxide trap density ( ${N}_{{\text {OT}}})$ as compared to forming gas or O2 postmetallization anneals (PMA), indicating that metal-induced bandgap states at the gate metal/dielectric interface have a notable impact on Ge pMOS ${N}_{{\text {OT}}}$ . On the other hand, a tradeoff must be made between ${N}_{{\text {OT}}}$ and the equivalent oxide thickness when performing PMA under O2 or forming gas ambient.

Electrical Stability Impact of Gate Oxide in Channel Implanted SiC NMOS and PMOS Transistors

Operation of SiC MOSFETs beyond 300°C opens up opportunities for a wide range of CMOS based digital and analogue applications. However the majority of the literature focuses only on the optimization of a single type of MOS device (either PMOS or more commonly NMOS) and there is a lack of a comprehensive study describing the challenge of optimizing CMOS devices. This study reports on the impact of gate oxide performance in channel implanted SiC on the electrical stability for both NMOS and PMOS capacitors and transistors. Parameters including interface state density (Dit), flatband voltage (VFB), threshold voltage (VTH) and effective charge (NEFF) have been acquired from C-V characteristics to assess the effectiveness of the fabrication process in realising high quality gate dielectrics. The performance of SiC based CMOS transistors were analyzed by correlating the characteristics of the MOS interface properties, the MOSFET 1/f noise performance and transistor on-state stability at 300°C. The observed instability of PMOS devices is more significant than in equivalent NMOS devices. The results from MOS capacitors comprising interface state density (Dit), flatband voltage (VFB), threshold voltage (VTH) for both N and P MOS are in agreement with the expected characteristics of the respective transistors.

Fermi-level unpinning in Pt/Al2O3/GaSb PMOS capacitors by sulphurization and rapid thermal annealing of GaSb surfaces

A facile route to mitigate the Fermi-level pinning between a p-type GaSb semiconductor and an Al2O3 dielectric is proposed. Combination of the sulphurization of the GaSb surface and the subsequent rapid thermal annealing allowed for high quality GaSb/Al2O3 interfacial characteristics; the interfacial trap density value was ≤2.0 × 1012 cm−2 eV−1 in an energy range of 0.05 ≤ ET − Ev ≤ 0.45 eV for the PMOS capacitor via rapid thermal annealing at 575 °C. A physical rationale was given on the basis of the thermo-chemical conversion of Ga2O into Ga2O3 and the conformal elimination of Sb related elements and oxides on the GaSb surface.

Analytical Evaluation of Thermally Oxidized and Deposited Dielectric in NMOS-PMOS devices

We demonstrate the influence of enhancing the dielectric film used to form the gate in complimentary MOS circuits, designed for high temperature operation. The data show that the characteristics of both n-MOS and p-MOS capacitors and transistors have degraded capacitance characteristics in terms of the trapped charge in the dielectric, although the interface state density is dictated by the underlying stub oxide, at around 5×1012 cm-2eV-1. The use of a deposited oxide also reduces the variability in the critical electric field in the oxide, whilst maintaining a value of approximately 10MV cm-1. The channel mobility extracted from n-and pMOS transistors fabricated alongside the capacitors showed similar values, of approximately 3.8 cm2V-1s-1, which are limited by the high doping level in the epilayers used in this study.

Conduction Mechanisms at SiO<sub>2</sub>/4H-SiC Interfaces in MOS-Based Devices Subjected to Post Deposition Annealing in N<sub>2</sub>O

This paper reports on the conduction mechanisms through the gate oxide and trapping effects at SiO2/4H-SiC interfaces in MOS-based devices subjected to post deposition annealing in N2O. The phenomena were studied by temperature dependent current–voltage measurements. The analysis of both n and p-MOS capacitors and of n-channel MOSFETs operating in the “gate-controlled-diode” configuration revealed an anomalous hole conduction behaviour through the SiO2/4H-SiC interface, with the onset of current conduction moving towards more negative values during subsequent voltage sweeps. The observed gate current instabilities upon subsequent voltage sweeps were deeply investigated by temperature dependent cyclic gate current measurements. The results were explained by the charge-discharge mechanism of hole traps in the oxide.

Slow response in gate current–voltage characteristics of metal–oxide–semiconductor structures on the 4H-SiC face

We have investigated the gate current–voltage (Ig–Vg) characteristics of n-channel metal–oxide–semiconductor field-effect transistors (MOSFETs) and p-MOS capacitors on the 4H-SiC face. The gate current response to a change in gate voltage has a very slow part, which has been considered to be due to slow traps in the oxide near the SiO2–SiC interface. However, we found that the slow response can be explained by fast interface traps if the traps have a relatively large concentration. Carrier injection into the interface traps results in a change in the surface potential, and this suppresses the further injection of carriers. This new model can explain many electrical properties such as the constant-current behavior in the Ig–Vg characteristics, which was confirmed by one-dimensional (1D) device simulation. According to this model, the interface traps will not be occupied up to the surface Fermi level within the general time scale of the measurement. In spite of the arguments described above, slow traps also probably exist near the interface between SiO2 and SiC.

Communication—Anomalous Shift of the Capacitance-Voltage Characteristics Obtained for p-MOS Capacitors with a Tin-Doped Indium Oxide Gate

Properties of low-threshold silicon p-MOS capacitors with tin-doped indium oxide (ITO) gates have been investigated. A shift of the capacitance-voltage (C-V) characteristics after annealing the capacitors in an oxygen atmosphere was observed. An anomalous shift of the C-V characteristics is discussed based on the possible presence of negative charge at the ITO-silicon dioxide interface that comes from the diffusion of indium atoms into the silicon dioxide at annealing temperatures above 400°C.

DLTS analysis of amphoteric interface defects in high-TiO2 MOS structures prepared by sol-gel spin-coating

High-κ TiO2 thin films have been fabricated from a facile, combined sol – gel spin – coating technique on p and n type silicon substrate. XRD and Raman studies headed the existence of anatase phase of TiO2 with a small grain size of 18 nm. The refractive index ‘n’ quantified from ellipsometry is 2.41. AFM studies suggest a high quality, pore free films with a fairly small surface roughness of 6 Å. The presence of Ti in its tetravalent state is confirmed by XPS analysis. The defect parameters observed at the interface of Si/TiO2 were studied by capacitance – voltage (C – V) and deep level transient spectroscopy (DLTS). The flat – band voltage (VFB) and the density of slow interface states estimated are – 0.9, – 0.44 V and 5.24×1010, 1.03×1011 cm−2; for the NMOS and PMOS capacitors, respectively. The activation energies, interface state densities and capture cross – sections measured by DLTS are EV + 0.30, EC – 0.21 eV; 8.73×1011, 6.41×1011 eV−1 cm−2 and 5.8×10−23, 8.11×10−23 cm2 for the NMOS and PMOS structures, respectively. A low value of interface state density in both P- and N-MOS structures makes it a suitable alternate dielectric layer for CMOS applications. And also very low value of capture cross section for both the carriers due to the amphoteric nature of defect indicates that the traps are not aggressive recombination centers and possibly can not contribute to the device operation to a large extent.

Improved Structural and Electric Characterstics of Al/ALD-HfO2/Ge MOS Capacitor by Germanium Dioxide and Germanium Oxynitride as Interfacial Layer

In this work HfO2 thin films has been deposited on Ge substrate by ALD with thickness of 9.77 nm. Thickness evaluation of film was done by Spectroscopic Ellipsometer (SE) and Filmetrics Reflectometer whereas chemical compositions and the states of the elements of the films were investigated by X-ray Photoelectron Spectroscopy (XPS). High-frequency Capacitance-Voltage (C-V), Conductance-Voltage (G-V) techniques and Current-Voltage (I-V) measurement were used to obtain the electrical properties of the high-k MOS capacitor. Different Ge surface cleaning methods preceding high-k ALD have been used for reducing oxide traps. Rapid Thermal Oxidation (RTO) and Rapid Thermal Nitridation (RTN) have been used to form the gate interlayer (IL) of GeO2 and GeON for the gate stack of P-MOS capacitor. By assimilating a thin GeON interlayer, excellent MOS capacitors with very small capacitance–voltage hysteresis and low gate leakage have been demonstrated. Physical and Electrical characterization investigates the quality of the oxynitride interlayer and low interface trap density (Dit ≈ 0.63×1012eV-1cm-2) in case of GeON/Ge which is improved as compared to the GeO2/Ge interface (Dit ≈ 2.53×1013 eV-1cm-2). Further electrical characterizations of HfO2 gate dielectric MOS capacitors deposited by the ALD using RTO & RTN as IL were investigated for the measurement of EOT and Qeff. The calculated EOT and Qeff values for GeON/Ge are 3.23 nm and 16.92×1012 cm-2 respectively which is better in comparison with GeO2 and as deposited samples.

A 1.0 V 12-bit 500 kS/s SAR ADC With Background Calibration for BioMedical Application

A 1.0 V 12-bit 500 kS/s SAR ADC With Background Calibration for BioMedical Application