Plasma Nitrided Oxide Research Articles

Copper and Nitrogen Co-Doping Effect on Visible-Light Responsive Photocatalysis of Plasma-Nitrided Copper-Doped Titanium Oxide Film

In order to clarify the visible-light responsive photocatalysis of TiO2 co-doped with Cu and N atoms, plasma-nitridation was taken place to Cu-doped TiO2 film. Cu-doped TiO2 films were prepared by dip-coating method and they were nitrided by nitrogen plasma in the plasma-enhanced CVD system. Cu-doped TiO2 films before and after plasma-nitridation show similar X-ray diffraction peaks of anatase TiO2. XPS analysis reveals that the ionic states of Ti and Cu in the Cu-doped TiO2 films are Ti4+ and Cu+, respectively. After nitrogen plasma treatment, oxygen atoms are released by substitution of nitrogen atoms in the TiO2 matrix, so that Cu+ is oxidized to generate Cu2+ and at the same time oxygen vacancy is formed. The absorption edge of both Cu-doped and plasma-nitrided Cu-doped TiO2 did red shift. Visible-light responsive photocatalytic activity of the Cu-doped TiO2 film degraded after nitrogen plasma treatment.

Behavior of incorporated nitrogen in plasma-nitrided silicon oxide formed by chemical vapor deposition

The behavior of nitrogen (N) atoms in plasma-nitrided silicon oxide (SiO2) formed by chemical vapor deposition (CVD) was characterized by physical analysis and from electrical properties. The changes in the chemical bonding and distribution of N in plasma-nitrided SiO2 were investigated for different subsequent processes. N–Si3, N–Si2O, and N2 are formed in a SiO2 film by plasma nitridation. N2 molecules diffuse out during annealing at temperatures higher than 900 °C. NH species are generated from N2 molecules and H in the SiO2 film with subsequent oxide deposition using O3 as an oxidant. The capacitance–voltage (C–V) curves of metal–oxide–semiconductor (MOS) capacitors are obtained. The negative shift of the C–V curve is caused by the increase in the density of positive fix charge traps in CVD-SiO2 induced by plasma nitridation. The C–V curve of plasma-nitrided SiO2 subjected to annealing shifts to the positive direction and that subjected to the subsequent oxide deposition shifts markedly to the negative direction. It is clarified that the density of positive charge fixed traps in plasma-nitrided SiO2 films decrease because the amount of N2 molecules is decreased by annealing, and that the density of traps increases because NH species are generated and move to the interface between SiO2 and the Si substrate with the subsequent oxide deposition.

Negative Bias Temperature Instability for Sputtering Modification in a TiN Diffusion Barrier of p+ Polysilicon Gate Stack in 50-nm DRAM Technology

Negative bias temperature instability (NBTI) in plasma-nitrided oxide affected by the nitrogen incorporation of a TiN diffusion barrier layer of gate stack is first proposed. In the standard 50-nm DRAM technology, three different groups including high, medium, and low N2 flow were deposited by sputtering to investigate in this paper. The high N2 flow group was with higher drive current and higher transconductance, but worse NBTI performance in pMOSFETs than that of the low N2 flow group. Boron (B) concentration at the bottom of p+ polycrystalline silicon (poly-Si) for the high N2 flow group is 5.4% higher than that for the low N2 flow group, which is verified by the secondary ion mass spectroscopy depth profile. A vertical electric field across gate nitrided oxide enhanced by high B concentration in the interface of p+ poly-Si/nitrided oxide resulted in the degradation of NBTI and time-dependent dielectric breakdown of the high N2 flow group. However, process optimization still needs to be studied between device performance and reliability of pMOSFETs in future generation.

Physical understanding of negative bias temperature instability below room temperature

The physical mechanism of VT degradations under negative bias temperature stress below room temperature has been studied for SiO2 and plasma nitrided oxide (PNO-based) pMOSFETs. It is found that VT degradations in both devices exhibit strong dependence on the electric field and temperature. The analysis shows that this strong dependence follows multi-phonon field-assisted tunneling theory, which indicates the inelastic hole trapping mechanism in the low temperature negative bias temperature instability (NBTI). On the other hand, by applying a low temperature sweeping technique, the energy distribution of these NBTI-induced hole traps below room temperature is indentified. The energy distribution of hole traps has two obvious peaks, one in the lower and one in the upper half of the silicon band gap. Both peaks gradually develop with increasing the stress time and temperature. We attempt to compare the energy profile for SiO2 and PNO devices to identify the trap precursors in NBTI below room temperature.

ChemInform Abstract: Electrically Detected Magnetic Resonance in Dielectric Semiconductor Systems of Current Interest

AbstractReview: 30 refs.

Effect of Nitrogen Concentration on Low-Frequency Noise and Negative Bias Temperature Instability of p-Channel Metal–Oxide–Semiconductor Field-Effect Transistors with Nitrided Gate Oxide

In this paper, the dependence of negative bias temperature instability (NBTI) and low-frequency noise characteristics on the various nitrided gate oxides is reported. The threshold voltage shift (ΔVT) under NBTI stress for thermally nitrided oxide (TNO) was greater than that of plasma nitrided oxide (PNO), whereas the slopes of ΔVT versus stress time for PNO were similar to those for TNO. The flicker noise (1/f noise) characteristic of PNO was better than that of TNO by about 1 order of magnitude, although the 1/f noise of PNO showed almost the same dependence on the frequency as that of TNO. The carrier number fluctuation model due to the trapping and detrapping of electrons in oxide traps was found to be a dominant mechanism of flicker noise. The probability of the generation of drain current random telegraph signal (ID–RTS) noise shows similar values (70–78%) for all nitrided oxides, which shows that the generation of RTS noise is not greatly affected by the nitridation method or nitrogen concentration.

Process optimization of plasma nitridation SiON for 65 nm node gate dielectrics

The gate leakage current and reliability concern become more serious due to the aggressive scalingdown of the gate oxide thickness. Developing advanced gate dielectrics process for mass production is essential in China. In this paper, the gate leakage current reduction and reliability optimization for plasma nitridation SiON aimed at 65 nm node CMOS application was explored. A three-step fabrication process based on single wafer tools for plasma nitridation SiON has been demonstrated. The effects of each process condition on the electrical and reliability characteristics of plasma nitridation SiON have been investigated in terms of nitrogen concentration, equivalent oxide thickness(EOT), gate leakage current, mobility, time-dependent dielectric breakdown (TDDB) and negative bias temperature instability (NBTI). The optimized plasma nitrided oxide demonstrated good gate leakage reduction and high carrier mobility without sacrificing the reliability performance. This optimized plasma nitridation process has been implemented into the mass production to meet the throughput and reliability requirement.

Characterization of Near-Interface Oxide Trap Density in Nitrided Oxides for Nanoscale MOSFET Applications

This paper presents the depth profile of oxide trap density, extracted from the dual gate processed thermally grown oxide in NO ambient and remote plasma nitrided oxides by using multifrequency and multitemperature charge pumping technique in conjunction with the tunneling model of trapped charges. Nitrided oxide is widely used to improve the reliability of nanoscale MOSFETs because it can decrease the degradation of gate oxide due to the generation of traps therein. Based on the measurement, the optimum nitrogen concentration in such typical nitrided process is discussed in correlation with the gate oxide thickness for nanoscale CMOSFETs.

Extraction of Interface-States Energy Distribution in Nitrided and Pure Gate Dielectrics for Metal Oxide Semiconductor Field Effect Transistor Applications

The interface states have been one of the main reliability concerns for nano-scale metal oxide semiconductor field effect transistors (MOSFETs). Especially, the stress induced interface states generation is very important. For quantitatively clarify, the high-frequency charge pumping technique is presented and it has better accuracy and easier than former charge pumping method, which needs variable rise and fall times of gate pulse. Furthermore, it can reject border traps effect. Using the presented method, the energy distribution of interface states was extracted and the Fowler–Nordheim stress induced energy level of interface states was profiled in pure silicon dioxide and finely engineered remote plasma nitrided oxide. The technique is well suited for investigating the nano-scale MOSFET reliabilities.

Evidence on p -MOSFET recovery characteristics under NBT stress

An investigation on the recovery characteristics of p-MOSFET with ultra-thin decoupled plasma nitrided gate oxide under negative bias temperature (NBT) stress is presented. The electron trapping assisted NBTI recovery mechanism is proposed with new evidence on the dependence of recovery rate on source/drain voltage, i.e. gate oxide field. Further, the findings about the different gate current behaviour and the source/drain voltage dependency indicate that the relaxation of positive charge, instead of interface trap, is the major component in the NBTI recovery stage.

Isolation of NBTI Stress Generated Interface Trap and Hole-Trapping Components in PNO p-MOSFETs

In this paper, a simple phenomenological technique is used to isolate the hole-trapping and interface trap generation components during negative bias temperature instability (NBTI) stress in plasma nitrided oxide (PNO) p-MOSFETs. This isolation methodology reconciles the apparent differences between experimentally measured NBTI power-law time exponents obtained by ultrafast on-the-fly IDLIN method, which are the ones obtained using slightly delayed but very long-time measurements, and the corresponding exponents predicted by the reaction-diffusion model. A systematic validation of the isolation technique is provided through degradation data taken over a broad range of operating conditions and a wide variety of PNO processes, to establish the robustness and uniqueness of the separation procedure.

A Comparative NBTI Study of $\hbox{HfO}_{2}$, $\hbox{HfSiO}_{x}$, and SiON p-MOSFETs Using UF-OTF $I_{\rm DLIN}$ Technique

The time, temperature, and oxide-field dependence of negative-bias temperature instability is studied in HfO2/TiN, HfSiOx/TiN, and SiON/poly-Si p-MOSFETs using ultrafast on-the-flyI DLIN technique capable of providing measured degradation from very short (approximately microseconds) to long stress time. Similar to rapid thermal nitrided oxide (RTNO) SiON, HfO2 devices show very high temperature-independent degradation at short (submilliseconds) stress time, not observed for plasma nitrided oxide (PNO) SiON and HfSiOx devices. HfSiOx shows lower overall degradation, higher long-time power-law exponent, field acceleration, and temperature activation as compared to HfO2, which are similar to the differences between PNO and RTNO SiON devices, respectively. The difference between HfSiOx and HfO2 can be attributed to differences in N density in the SiO2 IL of these devices.

A study on the electrical properties of plasma nitrided oxide gate dielectric in flash memory

In this paper, we address the effect of plasma nitridation on the gate dielectric in terms of device characteristics of an NMOS/PMOS transistor. Firstly, boron segregation due to plasma nitridation near Si/SiO2 interface and bulk Si is experimentally characterised by 1D SIMS, and its profile is reproduced in simulation of which parameters for boron diffusion are accurately calibrated through a comprehensive calibration process. Secondly, the electrical behaviour of NMOS/PMOS transistor with plasma nitride gate dielectric is verified, observing uncommon behaviour of C-V diagram in the case of buried-channel PMOS transistor. We prove that an excessive amount of interface traps generated by plasma nitridation influence abnormal electrical behaviour of the NMOS/PMOS transistor.

Optimization of Gate Leakage and NBTI for Plasma-Nitrided Gate Oxides by Numerical and Analytical Models

Reduction in static-power dissipation (gate leakage) by using nitrided oxides comes at the expense of enhanced negative-bias temperature instability (NBTI). Therefore, determining the nitrogen content in gate oxides that can simultaneously optimize gate-leakage and NBTI degradation is a problem of significant technological relevance. In this paper, we experimentally and theoretically analyze wide range of gate-leakage and NBTI stress data from a variety of plasma-oxynitride gate dielectric devices to establish an optimization scheme for gate-leakage and NBTI degradation. Calculating electric fields and leakage current both numerically and using simple analytical expressions, we demonstrate a design diagram for arbitrary nitrogen concentration and effective oxide thickness that may be used for process and IC design.

Investigation of Device Performance and Negative Bias Temperature Instability of Plasma Nitrided Oxide in Nanoscale p-Channel Metal–Oxide–Semiconductor Field-Effect Transistor's

In this paper, we investigated the device performance and negative bias temperature instability (NBTI) degradation for thermally nitrided oxide (TNO) and plasma nitrided oxide (PNO) in nanoscale p-channel metal oxide semiconductor field effect transistor (PMOSFET). PNOs show the improvement of dielectric performance compared to TNO with no change of the device performance. PNOs also show the improvement of NBTI immunity than TNO at low temperature stress, whereas NBTI immunity of PNO with high N concentration can be worse than TNO at high temperature stress. Recovery effect of NBTI degradation of PNO is lower than that of TNO and it is increased as the N concentration is increased in PNO because the dissociated Si dangling bonds and generated positive oxide charges are repassivated and neutralized, respectively. Moreover, complete recovery of ΔVth is dominated by neutralization of positive oxide charges. Therefore, N contents at polycrystalline Si/SiO2 interface as well as N contents at Si/SiO2 interface can affect significantly on NBTI degradation and recovery effect.

Atomic-scale defects involved in the negative-bias temperature instability

This paper examines the atomic-scale defects involved in a metal-oxide-silicon field-effect-transistor reliability problem called the negative-bias temperature instability (NBTI). NBTI has become the most important reliability problem in modern complementary-metal-oxide-silicon technology. Despite 40 years of research, the defects involved in this instability were undetermined prior to this paper. We combine DC gate-controlled diode measurements of interface-state density with two very sensitive electrically detected magnetic-resonance measurements called spin-dependent recombination (SDR) and spin-dependent tunneling (SDT). An analysis of these measurements provides an identification of the dominating atomic-scale defects involved in NBTI in pure- and plasma-nitrided oxide (PNO)-based devices. We are also able to observe atomic-scale defects involved in HfO2-based devices (although a definitive identification of the dominating defects structure was not possible). Our results in pure- devices indicate an NBTI mechanism which is dominated by the generation of Pb0 and Pb1 interface-state defects. (Pb0 and Pb1 are both silicon dangling-bond defects, in which the central silicon is back-bonded to three other silicon atoms precisely at the interface). This observation is consistent with what most NBTI researchers have assumed. However, our observations in PNO devices contradict with what most NBTI researchers had previously assumed. We demonstrate that the dominating NBTI-induced defect in the plasma-nitrided devices is fundamentally different than those observed in pure-based devices. Our measurements indicate that the new plasma-nitrided NBTI-induced defect's physical location extends into the gate dielectric. The defect participates in both SDR and SDT. Our SDR results strongly indicate that the plasma-nitrided defect has a density of states which is more narrowly peaked than that of centers and is near the middle of the band gap. The high sensitivity of our SDT measurements allow an identification of the physical and chemical nature of this defect through observations of hyperfine interactions. The defects are silicon dangling bonds, in which the central silicon is back-bonded to nitrogen atoms. We call these NBTI-induced defects centers because of the similarities to the centers observed in silicon nitride (the silicon-nitrided center is also a silicon dangling bond in which the silicon atom is back-bonded to nitrogen atoms). The defect identification in plasma-nitrided devices helps to explain the following phenomena: (1) NBTI's enhancement in plasma-nitrided devices; (2) conflicting reports of NBTI-induced interface states and/or bulk traps; and (3) fluorine's ineffectiveness in reducing NBTI in plasma-nitrided devices. We also observe the atomic-scale defects involved in NBTI in HfO2-based devices and find that short- and long-term stressing generates different defects and that these defects are different than those observed in the SiO2 and plasma-nitrided devices. Our results also suggest that the NBTI-induced defects in these devices are physically located in the interfacial layer (not at the interface).

Nano-scale PMOSFET에서 Plasma Nitrided Oixde에 대한 소자 특성의 의존성

In this paper, the reliability (NBTI degradation: ) and device characteristic of nano-scale PMOSFET with plasma nitrided oxide (PNO) is characterized in depth by comparing those with thermally nitrided oxide (TNO). PNO case shows the reduction of gate leakage current and interface state density compared to TNO with no change of the characteristics. Gate oxide capacitance (Cox) of PNO is larger than TNO and it increases as the N concentration increases in PNO. PNO also shows the improvement of NBTI characteristics because the nitrogen peak layer is located near the interface. However, if the nitrogen concentration in PNO oxide increases, threshold voltage degradation becomes more degraded by NBT stress due to the enhanced generation of the fixed oxide charges.

Observation of negative bias stressing interface trapping centers in metal gate hafnium oxide field effect transistors using spin dependent recombination

The authors combine metal oxide semiconductor (MOS) gated diode measurements and very sensitive electrically detected electron spin resonance measurements to detect and identify negative bias temperature instability (NBTI) generated defect centers in fully processed HfO2 pMOS field effect transistors. Both short and long term stressing defects are different from those generated by NBTI in Si∕SiO2 devices. The spectra generated by long term stressing differ from the short term stressing signals and are somewhat similar to those observed in plasma nitrided oxide Si∕SiO2 devices. The results suggest that NBTI defects are located in the interfacial SiO2 layer of these HfO2 devices.

Systematical Study of Reliability Issues in Plasma-Nitrided and Thermally Nitrided Oxides for Advanced Dual-Gate Oxide p-Channel Metal–Oxide–Semiconductor Field-Effect Transistors

In this study, we compared the effects of negative-bias temperature instability (NBTI) and hot-carrier injection (HCI) on the core and input/output (I/O) p-channel metal–oxide–semiconductor field-effect transistor (PMOSFET) fabricated using the different gate dielectrics of plasma nitrided oxide (PNO) and thermally nitrided oxide (TNO). The mobility and constant overdrive current of the PMOSFETs fabricated using PNO as a gate oxide material are about 30 and 23% higher than those of the devices fabricated using TNO, respectively. The core PMOSFETs fabricated using PNO show a better NBTI and HCI immunity than those fabricated using TNO owing to the lower nitrogen concentration at the SiO2/Si-substrate interface. However, the I/O PMOSFETs fabricated using PNO show a higher HCI-induced degradation rate because of a higher oxide bulk trap density but a better NBTI than the devices fabricated using TNO at a normal stressed bias due to a low interface trap density.

Effect of repetition of plasma nitride oxide integration

Effect of repetition of plasma nitride oxide integration was examined, because plasma nitrided oxide can be repeatedly used for multiple gate oxide structure and modified substrate technique. More localization of nitrogen on the oxide surface and re-arrangement of nitrogen-less interface are obtained by repetition of plasma nitride oxide integration. The structural and molecular changes in Si/oxide stack result in the improved channel mobility and the comparable saturated drive current. A 70% of gate leakage current density reduction is also obtained without drive current degradation, which is equivalent to about 5% of drive current improvement at a given gate leakage current density. The increase in nitride layer and oxide/interface layer could be estimated by using a schematic oxide thickness model.