Physical understanding of negative bias temperature instability below room temperature

Abstract

The physical mechanism of VT degradations under negative bias temperature stress below room temperature has been studied for SiO2 and plasma nitrided oxide (PNO-based) pMOSFETs. It is found that VT degradations in both devices exhibit strong dependence on the electric field and temperature. The analysis shows that this strong dependence follows multi-phonon field-assisted tunneling theory, which indicates the inelastic hole trapping mechanism in the low temperature negative bias temperature instability (NBTI). On the other hand, by applying a low temperature sweeping technique, the energy distribution of these NBTI-induced hole traps below room temperature is indentified. The energy distribution of hole traps has two obvious peaks, one in the lower and one in the upper half of the silicon band gap. Both peaks gradually develop with increasing the stress time and temperature. We attempt to compare the energy profile for SiO2 and PNO devices to identify the trap precursors in NBTI below room temperature.