Planar MOSFETs Research Articles

A New Technique for Mobility Extraction in MOSFETs in the Presence of Prominent Gate Oxide Trapping: Application to InGaAs MOSFETs

In the presence of prominent gate oxide trapping, the conventional technique for channel mobility extraction in MOSFETs based on ${I}$ – ${V}/{C}$ – ${V}$ measurements becomes inadequate. This is the consequence of two different effects associated with oxide traps: gate voltage stretch-out and electron trapping and detrapping in the oxide at the megahertz (MHz)-range frequencies that are commonly utilized. In thin-channel planar InGaAs MOSFETs, both effects are observed and found to result in a severe overestimation of mobile charge and subsequently an underestimation of mobility using ${I}$ – ${V}/{C}$ – ${V}$ . To address this issue, we demonstrate a new mobility extraction technique (RF- ${I}_{D}$ ) based on concurrent ${I}$ – ${V}$ and ${S}$ -parameter measurement in the gigahertz (GHz) regime that is largely immune to oxide trapping. Excellent agreement with Hall measurements as well as with theoretical predictions from Poisson–Schrodinger simulations gives confidence to the new technique. Importantly, the new technique is not limited to InGaAs planar MOSFETs, but applies to any device geometry and any material system. Promising mobility ~1100 cm2/ $\text{V}\cdot \text{s}$ is found in quantum-well planar InGaAs MOSFETs with a 4-nm-thick channel.

Symmetric Source and Drain Voltage Clamping Scheme for Complete Source–Drain Symmetry in Field-Effect Transistor Modeling

For structurally symmetric field-effect transistors with respect to the source and the drain, their models should be electrically symmetric about the source-drain interchange. This article shows that the commonly used drain-source voltage clamping technique breaks such a symmetry. This article then presents a symmetric source and drain voltage clamping scheme to solve the problem. The effectiveness of the new scheme is demonstrated by both the planar MOSFET model PSP and the FinFET model BSIM-CMG.

A Journey from Bulk MOSFET to 3 nm and Beyond

To overcome scaling issues such as controlling gate leakage, drain induced barrier lowering, higher subthreshold conduction, polysilicon gate depletion, and other short channel effects various engineering proposed. The gate dielectric, metal work function, and device structural engineering enabled the semiconductor industry to make a transition from the conventional planar MOSFET towards a revolutionary 3D tri-gate structure called FinFET. FinFET is one of the fundamental invention in the semiconductor industry, which replaced the planar CMOS technology around 22 nm technology. By following Moore’s law, it accelerated the scaling to 7 nm, but at 5 nm, in the same way, GAAFET replaced FinFET due to technological hurdles. Nanosheet, which is one type of GAAFET are in the recent trend. But researchers are trying to explore the possibilities to continue the miniaturization beyond 3 nm by combining the effect of non-silicon channel material such as Ge, InGaAs, or 2D materials with nanosheet, which will improve the functionality of the device while going down in the technology node. In this survey, an attempt has been made for the structure present till 7 nm process. Also, a few new proposals in research to take the scaling up to 3 nm and beyond are included. The future innovations may put an intercept on the slowing down of Moore’s law, and bring the miniaturization back in the track.

Low-Frequency Noise Characterization of Germanium n-Channel FinFETs

This article presents an experimental, room temperature, low-frequency noise characterization of germanium n-channel fin-field-effect transistors (finFETs) integrated on silicon. After determining the dominant mechanism in the noise spectrum, the main parameters associated with the noise mechanism are extracted and evaluated as a function of fin width from a planar-like (100 nm) up to narrow fin (20 nm) for 1- $\mu \text{m}$ length devices. The main findings are that the 1/ ${f}$ noise plays an important role in the Ge n-finFETs, whereby the trap density profiles in the gate-stack are quite uniform and have a lower level than in n-/p-channel Ge planar MOSFETs. In addition, a generation-recombination (GR) component was found in 160-nm-length devices, which is caused by GR centers located in the depletion region.

Third Quadrant Conduction Loss of 1.2–10 kV SiC MOSFETs: Impact of Gate Bias Control

The third quadrant (3rd-quad) conduction of power MOSFETs involves competing current sharing between the metal-oxide-semiconductor (MOS) channel and the body diode controlled by the gate bias (V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">G</sub> ). For 1.2 kV SiC planar MOSFETs, it is well known that a positive V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">G</sub> higher than the threshold voltage enables parallel conduction through both channels, which reduces the 3rd-quad voltage drop and conduction loss. This work, for the first time, unveils that this fact does not hold for higher voltage (e.g., 3.3 kV and 10 kV) SiC planar MOSFETs. By combining the static characterization, simulation, and modeling, it is revealed that, once the MOS channel turns on, the body diode in high-voltage MOSFETs turns on at a source-to-drain voltage (V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">SD</sub> ) much higher than the built-in potential of the PN junction. In 10 kV SiC MOSFETs, the body diode does not turn on over the entire practical V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">SD</sub> range if the MOS channel is on. As a result, the positive V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">G</sub> leads to completely unipolar conduction, which could induce a higher voltage drop than the bipolar body diode at high temperatures. A buck converter based on a 10 kV SiC MOSFET half-bridge module was built and tested, which validated that a negative V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">G</sub> control provides the smallest 3rd-quad voltage drop and conduction loss at high temperatures. Finally, based on the revealed physics for planar MOSFETs, the optimal V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">G</sub> control for the 3rd-quad conduction in trench MOSFETs is discussed. These results provide critical device understandings of 1.2-10 kV SiC MOSFETs and important application guidelines for 10 kV SiC MOSFETs.

Design and Simulation Analysis of Vertical Double-Gate MOSFET (VDGM) Structure for Nano-Device Application

Design and simulation analysis of vertical MOSFET structure with double gate structure on each side of insulating pillar for nanodevice applications is presented. The body doping effect on vertical channel for channel length, L g = 50nm and analyzing its effect towards such small devices was successfully performed. The analysis continued with the comparative investigation of device performance with conventional planar MOSFET as scaling L g down to 50nm. The final part evaluates the innovative design of incorporating dielectric pocket (DP) on top of vertical MOSFET turret with comprehensive device performance analysis as compared to standard vertical MOSFET in nanoscale realm. An optimized body doping for enhanced performance of vertical MOSFET was revealed. The vicinity of DP near the drain end is found to reduce the charge sharing effects between source and drain that gives better gate control of the depletion region for short channel effect (SCE) suppression in nanodevice structure.

Effect of Gate-Oxide Degradation on Electrical Parameters of Silicon Carbide MOSFETs

Although gate-oxide degradation occurs in both silicon (Si) and silicon carbide (SiC) MOSFETs, it requires a special attention in SiC MOSFETs. This is because the gate oxide in SiC MOSFETs is comparatively thinner than the gate oxide in Si MOSFETs, and thus, a higher electric field that appears across it could push the gate oxide to its reliability limit. While several electrical parameters have been identified as precursors (indicators) for monitoring the gate-oxide degradation process in Si MOSFETs, very few have been identified for their SiC counterparts. The purpose of this article is twofold. The first objective is to demonstrate that the three gate-oxide degradation precursors identified for Si MOSFETs: 1) threshold voltage, 2) gate-plateau voltage, and 3) gate-plateau time can also be extended to SiC MOSFETs. The second objective is to demonstrate analytically and experimentally that all three precursors increase in a linear-with-log-stress-time manner during gate-oxide degradation in both planar and trench-gate SiC MOSFETs. The increasing trends of precursors and their associated logarithmic time responses were experimentally verified by inducing accelerated gate-oxide degradation in two different commercial SiC MOSFETs (650-V, 70-A trench-gate MOSFETs and 1200-V, 19-A planar MOSFETs) under high temperatures of 150 and 125 °C, respectively.

Statistical Extraction of Normally and Lognormally Distributed Model Parameters for Power MOSFETs

In this paper, we propose a new statistical model parameter extraction method for compact power device models. While existing parameter extraction methods are only applicable for the parameters that follow normal distributions, the proposed method can simultaneously incorporate the model parameters that follow lognormal distributions. In addition, a set of dominant model parameters, which largely contributes to the characteristic variation of power MOSFETs, has been studied on the basis of the proposed statistical parameter modeling. Through the numerical analysis upon measured drain currents of planar and trench SiC power MOSFETs, we demonstrate that the fluctuation of the current characteristics can be represented by a small number of dominant parameters. In our example, threshold voltage and current scaling factor are identified to be particularly important to approximate the fluctuation of the current characteristics in both structures.

Stability Improvement of an Efficient Graphene Nanoribbon Field-Effect Transistor-Based SRAM Design

The development of the nanoelectronics semiconductor devices leads to the shrinking of transistors channel into nanometer dimension. However, there are obstacles that appear with downscaling of the transistors primarily various short-channel effects. Graphene nanoribbon field-effect transistor (GNRFET) is an emerging technology that can potentially solve the issues of the conventional planar MOSFET imposed by quantum mechanical (QM) effects. GNRFET can also be used as static random-access memory (SRAM) circuit design due to its remarkable electronic properties. For high-speed operation, SRAM cells are more reliable and faster to be effectively utilized as memory cache. The transistor sizing constraint affects conventional 6T SRAM in a trade-off in access and write stability. This paper investigates on the stability performance in retention, access, and write mode of 15 nm GNRFET-based 6T and 8T SRAM cells with that of 16 nm FinFET and 16 nm MOSFET. The design and simulation of the SRAM model are simulated in synopsys HSPICE. GNRFET, FinFET, and MOSFET 8T SRAM cells give better performance in static noise margin (SNM) and power consumption than 6T SRAM cells. The simulation results reveal that the GNRFET, FinFET, and MOSFET-based 8T SRAM cells improved access static noise margin considerably by 58.1%, 28%, and 20.5%, respectively, as well as average power consumption significantly by 97.27%, 99.05%, and 83.3%, respectively, to the GNRFET, FinFET, and MOSFET-based 6T SRAM design.

Total-Ionizing-Dose Effects on 3D Sequentially Integrated, Fully Depleted Silicon-on-Insulator MOSFETs

Effects of additional thermal budget associated with a three-dimensional (3D) fabrication sequence are evaluated for the total-ionizing dose radiation response of fully depleted silicon-on-insulator (FD-SOI) MOSFETs. Current-voltage and low-frequency (1/f) noise measurements are compared for (1) conventional planar FD-SOI MOSFETs, and (2) MOSFETs formed in the bottom layer of the 3D process and subjected to the process steps associated with formation of a second active layer. Similar radiation-induced voltage shifts and increases of 1/f noise are observed after irradiation for both types of structures. These similar changes in response show that the additional thermal processing involved with 3D fabrication has little effect on border-trap densities and radiation-induced charge trapping in gate and/or buried oxides of MOSFETs formed in the bottom layer of the 3D process.

Comparative Study of SiC Planar MOSFETs With Different p-Body Designs

Silicon carbide MOSFET has been commercialized for many years. Its performance is still improving especially for high-frequency application. High-frequency figure-of-merit (HF-FOM) ${R}{ \mathrm{\scriptstyle ON}}^\ast {C}_{\text {GD}}$ and ${R}_{ \mathrm{\scriptscriptstyle ON}}{}^\ast ~{Q}_{\text {GD}}$ were used for a comprehensive evaluation of the performance of MOSFET. In this article, SiC planar MOSFETs with different p-body designs were comparatively studied. A new planar MOSFET with buffered gate and thick central oxide gate structure (TCOX-MOS) was proposed to further improve the gate oxide electric field in OFF-state and HF-FOM. Compare to the conventional planar MOSFET (C-MOS), the maximum gate oxide electric field, gate–drain charge, and HF-FOM ( ${R}_{ \mathrm{\scriptscriptstyle ON}} {}^{\ast } {Q}_{\text {GD}}$ ) of TCOX-MOS are 32%, 83%, and 84% lower, respectively. Furthermore, TCOX-MOS shows less short-channel effects by better channel shielding structure. The results show that TCOX-MOS is a more attractive device structure.

Analytical Model Developed for Precise Stress Estimation of Device Channel Within Advanced Planar MOSFET Architectures

An analytical model for the precise stress estimation of device channels is developed and demonstrated in this article. The resultant stress magnitude under considered stress resources, including strained source/drain (S/D) and intrinsic stressed shallow trench isolation (STI), is carefully predicted and compared. The calculated accuracy of the presented model is validated through finite element simulation by a given example of the Si/SiGe material system arranged in S/D local regions and surrounded in the STI field. The rapid prognosis ability of the proposed model is performed on Si, Ge, and group III–V channels of nano-scaled transistors under specifically designed stressors. The S/D dependence of performance variety for all considered device materials can be directly estimated by changing the designed S/D length substituted into the analytical model. Moreover, the variations in induced mobility gain are further quantified using stress-piezoresistance relation. The analytic results indicate that the strained Ge pMOSFET outperforms other strained devices, such as Si and In0.53Ga0.47As channel materials, while identically designed strained level resulting from the lattice mismatch of S/D stressors is considered. Furthermore, the unstrained GaAs-based nMOSFET integrated with lattice-matched S/D Ge, indicating its superior electron mobility as compared with the S/D strained Si and Ge nMOSFETs owing to its advanced initial mobility. Accordingly, the systematically analytic flow of stress-induced device performance prediction is demonstrated via the present analytical solution integrated with corresponding piezoresistance models.

NCFET-Based 6-T SRAM: Yield Estimation Based on Variation-Aware Sensitivity

The key feature of NCFET (negative capacitance field effect transistor) is its sub-threshold slope (SS) < 60 mV/decade at 300 K. In this work, the n-type NCFET (i.e., pull-down (PD) and passgate (PG) transistor in six-transistor (6T) SRAM bit-cell) has SS of 53.92 mV/decade, and the p-type NCFET (i.e., pull-up (PU) transistor in the 6T SRAM bit-cell) has SS of 58.96 mV/decade. In the NCFET-based SRAM cell (vs. conventional SRAM cell with conventional planar bulk MOSFETs), its read (hold)-stability and write-ability are evaluated by the metric of read static noise margin (SNM) and write-ability current (Iw), respectively. Then, under process-induced random variation, sensitivities of SNM and Iw are extracted. Finally, the yield of NCFET-based SRAM array (vs. conventional SRAM array) is quantitatively estimated using the cell-sigma.

2.3 kV 4H-SiC Accumulation-Channel Split-Gate Planar Power MOSFETs With Reduced Gate Charge

2.3 kV 4H-SiC split-gate (SG) planar accumulation-channel power MOSFETs have been successfully manufactured in a 6 inch commercial foundry with good parametric distributions. The measured electrical characteristics of these devices are compared with conventional ACCUFETs manufactured with the same cell-pitch and process to quantify the improved performance. The gate charge and high-frequency figures-of-merit (HF-FOM) of the 2.3 kV SG-MOSFETs were experimentally verified to be a factor of 1.8x better than that of the conventional MOSFETs with no difference in specific on-resistance.

An investigation on a triple material double gate cylindrical gate all around (TMDG-CGAA) MOSFET for enhanced device performance

The present work investigates the Triple Material Double Gate Cylindrical Gate All Around (TMDG-CGAA) MOSFET in the nanometer regime to improve the device performance. Electrical parameters of TMDG-CGAA MOSFET are investigated under varying physical conditions like channel length, channel thickness, oxide thickness, and core diameter. For various parameters like drain current, threshold voltage, DIBL, and transconductance the TMDG-CGAA MOSFETs are evaluated. The comparison has been done among the SG-CGAA MOSFET, DG-CGAA MOSFET, and TMDG-CGAA MOSFET by using the same device parameters. The proposed structure TMDG-CGAA MOSFET has been validated by a device simulator named as 3D ATLAS tool. The device performance enhances by incorporating three materials at the gate electrode in the DG-CGAA MOSFET. In the planar MOSFET devices the SCEs enhances and also the threshold voltage is rolling off due to the reduced potential barrier between source and drain. But in the proposed structure the threshold voltage increases in the nanometer region also due to its cylindrical geometry. The drain current, transconductance also improves in comparison with the SG-CGAA MOSFET and DG-CGAA MOSFET. The SCE like DIBL decreases in the proposed structure. So overall the proposed structure shows better device performance with fast switching and lower cost.

SiC Planar MOSFETs With Built-In Reverse MOS-Channel Diode for Enhanced Performance

In this paper, the SiC planar MOSFET with built-in reverse MOS-channel diode (SiC MCDMOSFET) is investigated utilizing TCAD simulation tools. When the device is working as a freewheeling diode, the operation of the parasitic body diode is suppressed effectively due to the lower threshold voltage of the MCD. Therefore, the bipolar degradation issue can be completely solved. In addition, the SiC MCD-MOSFET is featuring superior dynamic characteristics. The input capacitance (CISS), reverse transfer capacitance (C RSS ), gate charge (Q G ) and gate-to-drain charge (Q GD ) are reduced by a factor of ~2, ~7, ~2 and ~10, respectively, as compared to the conventional SiC MOSFET (SiC C-MOSFET). Combined with the slightly increased on-resistance (R ON ), tremendously enhanced figures of merit (R ON × Q G and R ON × Q GD are decreased by a factor of 1.8 and 9, respectively) are obtained in the SiC MCD-MOSFET. The outstanding performance and easy-to-implement feature make the SiC MCD-MOSFET more attractive for further power electronic applications.

Performance and Reliability Review of 650 V and 900 V Silicon and SiC Devices: MOSFETs, Cascode JFETs and IGBTs

The future of power conversion at low-to-medium voltages (around 650 V) poses a very interesting debate. At low voltages (below 100 V), the silicon (Si) MOSFET reigns supreme and at the higher end of the automotive medium-voltage application spectrum (approximately 1 kV and above) the SiC power MOSFET looks set to topple the dominance of the Si insulated-gate bipolar transistor (IGBT). At very high voltages (4.5 kV, 6.5 kV and above) used for grid applications, the press-pack thyristor remains undisputed for current source converters and the press-pack IGBTs for voltage source converters. However, around 650 V, there does not seem to be a clear choice with all the major device manufacturers releasing different technology variants ranging from SiC Trench MOSFETs, SiC Planar MOSFETs, cascode-driven WBG FETs, silicon NPT and Field-stop IGBTs, silicon super-junction MOSFETs, standard silicon MOSFETs, and enhancement mode GaN high electron mobility transistors (HEMTs). Each technology comes with its unique selling point with gallium nitride (GaN) being well known for ultrahigh speed and compact integration, SiC is well known for high temperature, electro-thermal ruggedness, and fast switching while silicon remains clearly dominant in cost and proven reliability. This article comparatively assesses the performance of some of these technologies, investigates their body diodes, discusses device reliability, and avalanche ruggedness.

Junctionless MOS-Transistor with a Low Subthreshold Current

The junctionless MOS-transistors (junctionless MOSFET) have a number of advantages over conventional transistors in terms of the simplicity of design, manufacturing technology, and reduction of the impact of short-channel effects on the characteristics of the device. However, the well known experimental nanowire junctionless MOSFET have high subthreshold currents due to the appearance of the parasitic bipolar transistor effect in a closed state. The structural model of a planar SOI junctionless MOSFET by the technology standards of 90 nm and the route of mathematical simulation using the Synopsys Sentaurus TCAD environment are developed. The influence of the impurity concentration in a SOI silicon film of a junctionless MOSFET at the threshold voltage, saturation currents, and subthreshold currents is investigated. The research results reveal that at the impurity concentrations in the working channel of the device below 1017 cm–3, when the effect of band-to-band tunneling is absent and the parasitic bipolar transistor effect does not arise, the subthreshold currents decrease up to 10–13 A/μm, which is significantly lower than those of the conventional MOSFET, while maintaining the saturation currents at an acceptable level.

The Potential of SiC Cascode JFETs in Electric Vehicle Traction Inverters

The benefits of implementing silicon carbide (SiC) devices in electric vehicle (EV) powertrains have been widely reported in various studies. New generations of SiC devices including planar MOSFETs, trench MOSFETs, and more recently, cascode JFETs have been released by various manufacturers. SiC cascode devices comprise low-voltage silicon MOSFETs for gate driving and high-voltage depletion mode SiC JFETs for voltage blocking. These devices are particularly interesting, because they avoid the known reliability issues of SiC gate oxide traps resulting in threshold voltage drifts. In this article, an EV powertrain is simulated using experimental measurements of conduction and switching energies of various SiC devices including 650-V trench, 900-V planar, and 650-V cascode JFETs. Unlike in previous articles where losses are calculated using models based on datasheet parameters, here static and dynamic measurements on power devices at different currents and temperatures are used to calculate losses over simulated driving cycles. Field-stop IGBTs are also evaluated. The 3-phase, 2-level inverter model is electrothermal by accounting for the measured temperature dependence of the losses and uses accurate thermal networks derived from datasheets. The converter efficiency and the thermal performance are compared for each device technology. The results show that SiC cascode JFETs have great potential in EV powertrain applications.

Design and Optimization of 1.2-kV SiC Planar Inversion MOSFET Using Split Dummy Gate Concept for High-Frequency Applications

The gate architecture of a 1.2-kV SiC planar MOSFET is engineered to obtain the improved high-frequency figure of merit (HF-FOM) over the split-gate (SG) and planar-gate topology. In this article, we propose a device using the split dummy gate (SDG), which is in short with the source contact at zero potential. The device has a lower reverse transfer/feedback capacitance (C <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">rss</sub> or C <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">gd</sub> ) due to the formation of depletion width under SDG and lower gate-to-drain charge (Q <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">gd</sub> ) due to reduced overlap with the substrate leading to excellent HF-FOM(R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on,sp</sub> × C <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">gd</sub> and R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on,sp</sub> × Q <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">gd</sub> ). The essential electrical characteristics (such as Ron,sp, breakdown voltage (BV), and V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub> ) remain almost similar compared to the device without the dummy gate. The obtained HF-FOM(R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on,sp</sub> × Q <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">gd</sub> ) is 28.7× and 186× lower compared to the device with SG and planar-gate topology, respectively.Using calibrated Sentaurus TCAD simulations, the proposed SDG MOSFET has shown negligible Miller plateau (Q <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">gd</sub> ), reduced crowding of the electric field at the SG corner, and improved turn-on/off characteristics with a reduction in switching energies.