A Journey from Bulk MOSFET to 3 nm and Beyond

Abstract

To overcome scaling issues such as controlling gate leakage, drain induced barrier lowering, higher subthreshold conduction, polysilicon gate depletion, and other short channel effects various engineering proposed. The gate dielectric, metal work function, and device structural engineering enabled the semiconductor industry to make a transition from the conventional planar MOSFET towards a revolutionary 3D tri-gate structure called FinFET. FinFET is one of the fundamental invention in the semiconductor industry, which replaced the planar CMOS technology around 22 nm technology. By following Moore’s law, it accelerated the scaling to 7 nm, but at 5 nm, in the same way, GAAFET replaced FinFET due to technological hurdles. Nanosheet, which is one type of GAAFET are in the recent trend. But researchers are trying to explore the possibilities to continue the miniaturization beyond 3 nm by combining the effect of non-silicon channel material such as Ge, InGaAs, or 2D materials with nanosheet, which will improve the functionality of the device while going down in the technology node. In this survey, an attempt has been made for the structure present till 7 nm process. Also, a few new proposals in research to take the scaling up to 3 nm and beyond are included. The future innovations may put an intercept on the slowing down of Moore’s law, and bring the miniaturization back in the track.