Planar MOSFETs Research Articles

Methodology for Characterizing Degradation Locations of Planar and Trench Gate SiC Power Mosfets Under Repetitive Short-Circuit Stress

Methodology for Characterizing Degradation Locations of Planar and Trench Gate SiC Power Mosfets Under Repetitive Short-Circuit Stress

A Conclusive Algorithm with Kink Effects for Fitting 3-D FinFET and Planar MOSFET Characteristic Curves

A Conclusive Algorithm with Kink Effects for Fitting 3-D FinFET and Planar MOSFET Characteristic Curves

Impact of Layout Parameter Mismatches on Short Circuit Reliability of Parallel-Connected Planar, Trench, and Double-Trench SiC MOSFETs

Impact of Layout Parameter Mismatches on Short Circuit Reliability of Parallel-Connected Planar, Trench, and Double-Trench SiC MOSFETs

Comparison and analysis on static and dynamic performance of 1.2-kV SiC planar MOSFETs with different cell topologies

1.2-kV SiC MOSFETs with different cell topologies were fabricated based on the same design and process parameters in a commercial 6-inch SiC foundry. A series of comparative evaluations were conducted on the static and dynamic performance of SiC MOSFETs with common linear, island-shaped P+ linear, current sharing linear, and hexagonal cell topologies for the first time. The common linear cell topology has the lowest switching loss, but the highest on-resistance. The island-shaped P+ linear and current sharing linear cell topologies optimized the cell pitch, reduced the specific on-resistance by 9.68 %, but the freewheeling and surge capability of their body diode have been decreased. The current sharing linear cell topology has the highest Ciss/Crss, making it the lowest in crosstalk intensity. The hexagonal cell topology has the lowest on-resistance, but performs the worst in terms of blocking characteristics and switching losses.

A Unique Failure Mode of SiC MOSFETs under Accelerated HTRB

Device lifetime under reverse bias conditions is an important reliability concern for SiC devices. Provided that the termination structure is well designed, device failure in the active cell is driven by gate oxide breakdown due to the high field in the semiconductor and gate dielectric. For planar MOSFETs, the largest field occurs in the JFET region [1,2]. Standard HTRB testing is insufficient to estimate failure rates under operating conditions and hence testing under accelerated off-state conditions (ALT-HTRB) is required. This paper provides data, statistical analysis, failure analysis and finally a Weibull statistics-based temperature, Vd and stress time dependent model.

4H-SiC MOSFET Threshold Voltage Instability Evaluated via Pulsed High-Temperature Reverse Bias and Negative Gate Bias Stresses.

This paper presents a reliability study of a conventional 650 V SiC planar MOSFET subjected to pulsed HTRB (High-Temperature Reverse Bias) stress and negative HTGB (High-Temperature Gate Bias) stress defined by a TCAD static simulation showing the electric field distribution across the SiC/SiO2 interface. The instability of several electrical parameters was monitored and their drift analyses were investigated. Moreover, the shift of the onset of the Fowler-Nordheim gate injection current under stress conditions provided a reliable method to quantify the trapped charge inside the gate oxide bulk, and it allowed us to determine the real stress conditions. Moreover, it has been demonstrated from the cross-correlation, the TCAD simulation, and the experimental ΔVth and ΔVFN variation that HTGB stress is more severe compared to HTRB. In fact, HTGB showed a 15% variation in both ΔVth and ΔVFN, while HTRB showed only a 4% variation in both ΔVth and ΔVFN. The physical explanation was attributed to the accelerated degradation of the gate insulator in proximity to the source region under HTGB configuration.

One-Probe Nanoprobing of Power Devices and Electronic Packages

Results involving the use of a single nanoprobing contact are presented, on both a SiC planar MOSFET device, and a small system-in package. In both cases, mechanical polished samples were prepared, and then probed with a single contact. For the SiC MOSFET, the depletion zones were imaged while the samples were mounted on a 45 ° stub. Discussion of the different signals generated from Passive Voltage Contrast (PVC) and Electron Beam Induced Current (EBIC), as well as possible artifacts of sample grounding, are provided. For the package, Electron Beam Absorbed Current (EBAC) provided indication of connected features within the sample. The experiment showed the capability of measuring features across three orders of magnitude in size.

An analytical subthreshold I–V model of SiC MOSFETs

In this article, an analytical I–V model for calculating subthreshold current of SiC MOSFETs is presented. This model starts with planar MOSFETs and utilizes the one-dimensional Poisson’s equation to derive an analytical expression for the surface potential. Subsequently, it employs this expression as a foundation for subthreshold current calculations. Then the model is extended to DMOSFETs based on the fact that channel current formation mechanism of DMOSFETs is similar to that of planar MOSFETs. Comparative analysis of our model calculations with two-dimensional numerical simulation software reveals that our model exhibits a high degree of agreement in the case of planar MOSFETs and DMOSFETs. Interface traps were also considered in our analytical model, which agrees well with experimental data published elsewhere. Furthermore, the model retains a certain degree of accuracy and predictive capability even in the presence of short-channel effect. Our subthreshold model becomes complementary to existing models which only describe the I–V characteristics of SiC MOSFETs when the transistors operate above the threshold voltages.

Investigation on gate oxide reliability under gate bias screening for commercial SiC planar and trench MOSFETs

This paper evaluates the impact of the fast high gate-voltage screening technique on gate oxide reliability of commercial 1.2 kV 4H-SiC power metal-oxide-semiconductor field-effect transistors (MOSFETs) with planar and trench gate structures. The measurements are conducted on packaged devices with the intent that the results will be applicable to wafer-level screening. The threshold voltage (Vth) of SiC MOSFETs is measured before and after various screening treatments and recovery process. In addition, constant-voltage time-dependent dielectric breakdown (TDDB) measurements are performed on SiC MOSFETs to obtain the intrinsic lifetime of gate oxide. The objective of this study is to determine the optimal screening conditions and improve screening efficiency without degradation of gate oxide reliability, such as Vth shift and reduced oxide intrinsic lifetime. Due to the differences in the gate oxidation process and structural design of SiC planar and trench MOSFETs, the two types of devices exhibit different oxide reliability in the screening process. The recommended screening conditions obtained in this paper reveal that SiC trench MOSFETs can accept higher screening voltages compared to SiC planar MOSFETs. Hence, it can be concluded that more efficient screening techniques can be adopted for SiC MOSFETs with thicker gate oxide to meet the requirements of industrial applications.

An Investigation of Body Diode Reliability in Commercial 1.2 kV SiC Power MOSFETs with Planar and Trench Structures.

The body diode degradation in SiC power MOSFETs has been demonstrated to be caused by basal plane dislocation (BPD)-induced stacking faults (SFs) in the drift region. To enhance the reliability of the body diode, many process and structural improvements have been proposed to eliminate BPDs in the drift region, ensuring that commercial SiC wafers for 1.2 kV devices are of high quality. Thus, investigating the body diode reliability in commercial planar and trench SiC power MOSFETs made from SiC wafers with similar quality has attracted attention in the industry. In this work, current stress is applied on the body diodes of 1.2 kV commercial planar and trench SiC power MOSFETs under the off-state. The results show that the body diodes of planar and trench devices with a shallow P+ depth are highly reliable, while those of the trench devices with the deep P+ implantation exhibit significant degradation. In conclusion, the body diode degradation in trench devices is mainly influenced by P+ implantation-induced BPDs. Therefore, a trade-off design by controlling the implantation depth/dose and maximizing the device performance is crucial. Moreover, the deep JFET design is confirmed to further improve the body diode reliability in planar devices.

Suppression of threshold voltage shift due to positive bias stress in GaN planar MOSFETs by post-deposition annealing

Threshold voltage instability (shift) due to positive bias stress in GaN planar-gate MOSFETs was investigated. Gate dielectric (SiO2) was formed by remote-plasma-assisted CVD on homoepitaxial Mg-doped p-type GaN layers with Si-implanted n-type source and drain regions. The threshold voltage shift of 5.8 V was observed after a stress voltage of 30 V for a sample without post-deposition annealing (PDA). The threshold voltage shift was significantly reduced to 1.4 V for a sample with PDA (800 °C for 30 min). Stress time dependences up to 6000 s were measured, revealing that the main origin of the threshold voltage shift is electron trapping into near interface traps (NITs). These results suggest that PDA is effective for the reduction of the NITs.

The Analytical Models of Fringe Parasitic Capacitance of FinFET - A Review

When planar MOSFET encounters its own scaling limit, FinFET was introduced and successfully replaced the traditional MOSFET. FinFET owns its privilege over the planar MOSFET for its high tolerance to short channel effect. However, due to FinFET’s 3D structure, high parasitic capacitance compared to planar MOSFET significantly degrades the transistor speed because of RC delay. This paper provides a review on the fringe capacitance of FinFET device based on the accuracy to experimental data of the two-dimensional and three-dimensional analytical models. Those models take the external and internal parasitic capacitance component into account. The three-dimensional model outperforms the two-dimensional model in levels of precision but requires more parameters and time to establish.

Investigation on Degradation of 1200-V Planar and Trench SiC MOSFET Under Surge Current Stress of Body Diode

Investigation on Degradation of 1200-V Planar and Trench SiC MOSFET Under Surge Current Stress of Body Diode

Comprehensive Investigations on Recovery Characteristics of Bias Temperature Instability in Planar and Trench SiC MOSFETs

Comprehensive Investigations on Recovery Characteristics of Bias Temperature Instability in Planar and Trench SiC MOSFETs

Impact of Intrinsic Parameter Dispersion on Short-Circuit Reliability of Parallel-Connected Planar and Trench SiC MOSFETs

Impact of Intrinsic Parameter Dispersion on Short-Circuit Reliability of Parallel-Connected Planar and Trench SiC MOSFETs

Degradation Measurement and Modelling under Ageing in a 16 nm FinFET FPGA.

Most of the latest generation of integrated circuits use FinFET transistors for their performance, but what about their reliability? Does the architectural evolution from planar MOSFET to FinFET transistor have any effect on the integrated circuit reliability? In this article, we present a test bench we have developed to age and measure the degradation of 5103 ring oscillators (ROs) implemented in nine FPGAs with 16nm FinFET under different temperature and voltage conditions (Vnom≤Vstress≤1.3Vnom and 25°C≤Tstress≤115°C) close to operational conditions in order to predict reliability regarding degradation mechanisms at the transistor scale (BTI, HCI and TDDB) as realistically as possible. By comparing our initial RO measurements and the data extracted from Vivado, we will show that the performance of the nine FPGAs is between 50% and 70% of the best performance expected by Vivado. After 8000 h of ageing, we will see that the relative degradations of the RO are a maximum of 1%, which is a first indicator proving the FPGAs' good reliability. By comparing our results with similar studies on 28 nm MOSFET FPGAs, we will reveal that 16 nm FinFET FPGAs are more reliable. To be implemented in an FPGA, an RO uses logic resources (LUT) and routing resources. We will show that degradation in the two types of resources is different. For this reason, we will present a method for separating degradations in logical and routing resources based on RO degradation measures. Finally, we will model rising and falling edge propagation time degradations in an FPGA as a function of time, temperature, voltage, signal duty cycle and resources used in the FPGA.

GaAs MOSFETs with in situ Y2O3 dielectric: attainment of nearly thermally limited subthreshold slope and enhanced drain current via accumulation

Planar GaAs(100) depletion-mode (D-mode) MOSFETs as passivated with in situ deposited Al2O3/Y2O3 dielectric have shown enhancement of the drain current by 167% and 333% as the gate voltage (V g) increased from flat-band voltage (V fb), namely V g = V fb = 0.5 V to V g = 2 V and V g = 4 V, respectively, much higher than those in the previously published GaAs-based D-mode MOSFETs. In addition, we have achieved a high I on/I off of 107 and a subthreshold slope (SS) of 63 mV dec−1, which approaches the thermal limit of 60 mV dec−1 at 300 K and is the record-low value among planar (In)GaAs MOSFETs. Moreover, using the measured SS data, we have deduced an interfacial trap density (D it) of 4.1 × 1011 eV−1 cm−2 from our Al2O3/Y2O3/GaAs MOSFET, the lowest value among the planar (In)GaAs MOSFETs.

Modulation of Ciss of a 4H-SiC Planar MOSFET With a Shorter Sidewall and a Thicker Gate

Modulation of C_iss of a 4H-SiC Planar MOSFET With a Shorter Sidewall and a Thicker Gate

Design and Analysis of Electrical Characteristics of 14nm SOI-based Trigate Gaussian Channel Junctionless FinFET

Planar MOSFETs are reaching their physical limits. To overcome the limitations and improve channel gate control, FinFET technology, which uses many gate devices, is a superior choice while lowering the size of planar MOSFETs even further. In this paper, 14nm Silicon-On-Insulator-based Trigate Gaussian Channel Junctionless FinFET is presented. The gate length of 14nm is considered along with an Equivalent Oxide Thickness of 1nm, 5nm as fin width, and the work function of the gate metal is 4.75eV. The device architecture has a non-uniform doping profile (Gaussian distribution) across the fin’s thickness. It is devised to address the effects of Random Dopant Fluctuations such as channel mobility degradation in Junctionless FinFET based devices. The impact of fin height (Fh), gate dielectric and spacer dielectric on the Drain Induced Barrier Lowering, Subthreshold Swing, drain current of GC-JLFinFET is analyzed. The results show that the Ion=101.5μA/μm and Ion/Ioff is 3.2×107 are obtained for the proposed device structure compared to the existing structure, which has Ion/Ioff of 1.1x107. Furthermore, the proposed design shows better efficiency in short channel characteristics, namely DIBL=25.3 mV/V, Subthreshold Swing=63.88 mV/dec and Transconductance =3.621×105 S/μm. Thus the Gaussian Channel-based FinFET architecture can provide optimum results for Junctionless-based FinFET devices.

Total Ionizing Dose Hardening of Planar SOI MOSFET Through an Optimal Design Combining Embedded Void and H-Gate Structures

Total Ionizing Dose Hardening of Planar SOI MOSFET Through an Optimal Design Combining Embedded Void and H-Gate Structures