Suppression of threshold voltage shift due to positive bias stress in GaN planar MOSFETs by post-deposition annealing

Abstract

Threshold voltage instability (shift) due to positive bias stress in GaN planar-gate MOSFETs was investigated. Gate dielectric (SiO2) was formed by remote-plasma-assisted CVD on homoepitaxial Mg-doped p-type GaN layers with Si-implanted n-type source and drain regions. The threshold voltage shift of 5.8 V was observed after a stress voltage of 30 V for a sample without post-deposition annealing (PDA). The threshold voltage shift was significantly reduced to 1.4 V for a sample with PDA (800 °C for 30 min). Stress time dependences up to 6000 s were measured, revealing that the main origin of the threshold voltage shift is electron trapping into near interface traps (NITs). These results suggest that PDA is effective for the reduction of the NITs.