Planar Interconnects Research Articles

Scalable Fabrication of Large-Scale, 3D, and Stretchable Circuits.

Stretchable electronics have demonstrated excellent potential in wearable healthcare and conformal integration. Achieving the scalable fabrication of stretchable devices with high functional density is the cornerstone to enable the practical applications of stretchable electronics. Here, a comprehensive methodology for realizing large-scale, 3D, and stretchable circuits (3D-LSC) is reported. The soft copper-clad laminate (S-CCL) based on the "cast and cure" process facilitates patterning the planar interconnects with the scale beyond 1 m. With the ability to form through, buried and blind VIAs in the multilayer stack of S-CCLs, high functional density can be achieved by further creating vertical interconnects in stacked S-CCLs. The application of temporary bonding substrate effectively minimizes the misalignments caused by residual strain and thermal strain. 3D-LSC enables the batch production of stretchable skin patches based on five-layer stretchablecircuits, which can serve as a miniaturized system for physiological signals monitoring with wireless power delivery. The fabrications of conformal antenna and stretchable light-emitting diode display further illustrate the potential of 3D-LSC in realizing large-scale stretchable devices.

Bendability enhancement of 3D interconnections with out-of-plane corrugation for flexible hybrid electronics

This study focuses on enhancing the bendability of flexible interconnects with out-of-plane corrugation for flexible hybrid electronics. We propose two typical configurations of 3D corrugated interconnects: serpentine and trapezoidal. Three methods are introduced to fabricate these corrugated interconnects. The advantages and drawbacks of each fabrication strategy are discussed, and the impact of the 3D corrugation geometry and material on bendability is elucidated. In addition, the material properties of two types of negative photosensitive materials, SU-8 and F-PD (flexible-photoimageable dielectric), are compared. Results show that the resistance increase of 3D corrugated interconnects after a 5 mm radius bending test is drastically lower (by approximately 1900%–2000%) than that of conventional 2D planar interconnects.

High-performance, power-efficient three-dimensional system-in-package designs with universal chiplet interconnect express

Universal chiplet interconnect express (UCIe) is an open industry standard interconnect for a chiplet ecosystem in which chiplets from multiple suppliers can be packaged together. The UCIe 1.0 specification defines interoperability using standard and advanced packaging technologies with planar interconnects. Here we examine the development of UCIe as the bump interconnect pitches reduce with advances in packaging technologies for three-dimensional integration of chiplets. We report a die-to-die solution for the continuum of package bump pitches down to 1 µm, providing circuit architecture details and performance results. Our analysis suggests that—contrary to trends seen in traditional signalling interfaces—the most power-efficient performance for these architectures can be achieved by reducing the frequency as the bump pitch goes down. Our architectural approach provides power, performance and reliability characteristics approaching or exceeding that of a monolithic system-on-chip design as the bump pitch approaches 1 µm.

Aerodynamic slotted SIW-to-MS line transition using mitered end taper for satellite and RADAR communications

PurposeThis paper aims to present the design development and measurement of two aerodynamic slotted X-bands back-to-back planer substrate-integrated rectangular waveguide (SIRWG/SIW) to Microstrip (MS) line transition for satellite and RADAR applications. It facilitates the realization of nonplanar (waveguide-based) circuits into planar form for easy integration with other planar (microstrip) devices, circuits and systems. This paper describes the design of a SIW to microstrip transition. The transition is broadband covering the frequency range of 8–12 GHz. The design and interconnection of microwave components like filters, power dividers, resonators, satellite dishes, sensors, transmitters and transponders are further aided by these transitions. A common planar interconnect is designed with better reflection coefficient/return loss (RL) (S11/S22 ≤ 10 dB), transmission coefficient/insertion loss (IL) (S12/S21: 0–3.0 dB) and ultra-wideband bandwidth on low profile FR-4 substrate for X-band and Ku-band functioning to interconnect modern era MIC/MMIC circuits, components and devices.Design/methodology/approachTwo series of metal via (6 via/row) have been used so that all surface current and electric field vectors are confined within the metallic via-wall in SIW length. Introduced aerodynamic slots in tapered portions achieve excellent impedance matching and tapered junctions with SIW are mitered for fine tuning to achieve minimum reflections and improved transmissions at X-band center frequency.FindingsUsing this method, the measured IL and RLs are found in concord with simulated results in full X-band (8.22–12.4 GHz). RLC T-equivalent and p-equivalent electrical circuits of the proposed design are presented at the end.Practical implicationsThe measurement of the prototype has been carried out by an available low-cost X-band microwave bench and with a Keysight E4416A power meter in the microwave laboratory.Originality/valueThe transition is fabricated on FR-4 substrate with compact size 14 mm × 21.35 mm × 1.6 mm and hence economical with IL lie within limits 0.6–1 dB and RL is lower than −10 dB in bandwidth 7.05–17.10 GHz. Because of such outstanding fractional bandwidth (FBW: 100.5%), the transition could also be useful for Ku-band with IL close to 1.6 dB.

Enhanced thermal conductivity of polycarbonate‐based composites by constructing a dense filler packing structure consisting of hybrid boron nitride and flake graphite

AbstractIn this work, thermally conductive yet electrically insulative polycarbonate (PC)‐based composites with hybrid boron nitride (BN) and flake graphite (Gt) network structure were prepared by high shear injection molding process. A synergy in improving the thermal conductivity of PC was observed with the hybrid loading of BN and Gt. Results showed that the in‐plane thermal conductivity of PC/BN 30 wt%/Gt 16 wt% composite reached as high as 4.08 W/mK, which were 189% and 358% higher than that of PC/BN 30 wt% and PC/Gt 16 wt% composites, respectively. The preferred orientation of planar fillers and interconnection between added fillers were indispensable to the significant increase of in‐plane thermal conductivity, as corroborated by X‐ray diffraction, rheology and scanning electron microscope observations. Moreover, the electrical resistivity of PC/BN 30 wt%/Gt composites was higher than 1014 Ω cm, which shows potential application in thermal management areas such as advanced electronic devices and battery units among others.

Fluid Microchannel Encapsulation to Improve the Stretchability of Flexible Electronics (Adv. Mater. Technol. 6/2022)

Fluid Microchannel Encapsulation Method In article number 2101126, Yinji Ma, Xue Feng, and co-workers demonstrate a simple, generic fluid microchannel encapsulation method, which can substantially improve the stretchability of flexible electronics. In contrast to the conventional encapsulation method, the proposed method can increase the stretchability by over 100% for planar serpentine interconnects and by approximately 215% for a flexible LED device.

Design of fully adaptive routing and hybrid VC allocation in wireless NOC

Wireless network-on-chip (WiNoC) establishes a long-range single-hop wireless links on the base of the traditional planar metal interconnects network, which improve network performance in several aspects. The establishment of wireless link improves the diversity of path for packet transmitting, while simultaneously aggravates the deadlock problem, leading it to more complicated condemn. The traditional routing mechanism of wireless network on chip can avoid deadlock by sacrificing the adaptability of transmitting, which leads to unbalanced and insufficient use of limited on chip resources. In this paper, a fully adaptive routing mechanism is proposed to balance buffer utilization. At the same time, we proposed a hybrid virtual channel allocation strategy in order to make full use of buffer resources. For a large number of single-flit wired packets and wireless packets, more aggressive non-atomic allocation is adopted, and the remaining packets are arranged with atomic allocation to avoid potential deadlock. Experimental results showed that compared with the traditional deadlock solutions, the proposed scheme introduces less area and power consumption, and balances the utilization of buffer resources. Under the non-uniform Traffic Patterns, the proposed scheme has better performance in terms of delay and throughput, achieves 62.0% improvement compared to the traditional counterpart.

Embedded-Component Planar Fan-Out Packaging for Biophotonic Applications

Embedded-chip planar silver-elastomer interconnect technology is developed with flexible substrates and demonstrated for on-skin biophotonic sensor applications. This approach has several benefits and is also consistent with chip-thinning where the chip thickness is 100 microns and less. The key benefits from this approach arise because both the bottom and top sides are now available as flat surfaces for 3D integration of other components. It also results in the lowest electrical parasitics compared to flipchip with adhesives or printed-ramp interconnections with surface-assembled devices. Embedding of chips in flexible carriers was accomplished with direct screen-printed interconnects onto the chip pads in substrate cavities. Silver nanoflake-loaded polyurethane is utilized in the embedded-chip packages to provide the desired lower interconnect resistance and also reliability in flexible packages under deformed configurations. Viscoelastic models were utilized to model the interconnection stresses. Planar interconnects in flexible substrates are developed with conductive silver-loaded elastomer interconnects. This approach is compared to direct chip-on-flex assembly technology for reliability under bending and high-temperature storage. The embedded-chip technology is demonstrated through biophotonic sensor applications where light sources (LEDs) and photodetectors are embedded inside the package. Functional validation in bent configuration at low curvatures is shown by measuring pulse rate and muscle activity with human subjects. By extending this technology to nanowires in elastomers, further enhancement in electrical and reliability performance can be achieved.

Effects of La0.8Sr0.2MnO3 and Ag electrodes on bismuth-oxide-based low-temperature solid electrolyte oxygen generators

In this study, La 0.8 Sr 0.2 MnO 3 (LSM) was used as the ceramic electrode in a (Bi 1.50 Y 0.50 ) 0.98 Zr 0.04 O 3+δ (BYO)-based solid electrolyte oxygen generator (SEOG) and its performance was compared with that of a previously studied high-fire Ag electrode. Among La 0.6 Sr 0.4 Co 0.2 Fe 0.8 O 3 , LaNi 0.6 Fe 0.4 O 3 , Cu 1.4 Mn 1.6 O 4 , and LSM materials, only LSM materials did not trigger any chemical reaction or interdiffusion with BYO at temperatures up to 900 °C. Two cell designs, Cell A, with a Bi 1.71 Nb 0.25 Ba 0.04 O 3+δ (BBNO) interlayer and high-fire Ag electrode, and Cell B, with an LSM-BYO composite electrode, were obtained in this study. The cells were sandwiched between two modular SUS 316 planar interconnects using a ZnO–SiO 2 –Al 2 O 3 glass sealant to form the SEOG device. Although Cells A and B possessed similar ohmic resistance (R o ) values, the polarization resistance (R p ) values of Cell A were 3.6 times larger than those of Cell B. Furthermore, the stability study of the cells operated at 600 °C for 12 h revealed that R o increased from 0.79 to 3.17 Ω cm 2 and R p from 3.12 to 12.58 Ω cm 2 for the Cell A, while R o increased from 0.76 to 0.77 Ω cm 2 and R p from 0.87 to 1.12 Ω cm 2 for the Cell B. Therefore, minor variations in the R o and R p of Cell B indicate the excellent stability of the electrode. The degradation of Cell A was caused by the migration of Ag and formation of voids and cracks adjacent to the anode/electrolyte interface under the DC field. Furthermore, the Cell A experienced a decrease in faradaic efficiency for current densities greater than 0.20 A cm −2 owing to the partial decomposition of BYO at the cathode. In contrast, the Cell B generated an oxygen flux of 1.29 cm⋅min −1 at 600 °C. In addition, the faradaic efficiency of Cell B remained consistent for current densities up to 0.35 A cm −2 . Therefore, the SEOG using LSM-BYO as the cell electrode exhibited excellent stability and electrochemical performance.

Fused Deposition Modeling‐Based 3D‐Printed Electrical Interconnects and Circuits

Multimaterial 3D printing in electronics is expanding due to the ability to realize geometrically complex systems with simplified processes compared with conventional printed circuit board. Herein, the feasibility of using a copper‐based filament to realize 3D circuits with planar and vertical interconnections is presented. The resistivity of the tracks (1–3 mm wide) is studied with reference to printing parameters and orientation. Using lateral infill for 1 mm tracks offers lower resistance compared with longitudinal infill (≈75%). For wider tracks, the effect of infill orientation on resistance diminishes. The evaluation of tracks embedded in polylactic acid shows a drop in maximum current (to ≈11 mA) compared with exposed tracks (≈16 mA). There is no observed correlation between electrical performance and number of embedding layers. However, a significant correlation is observed between the tracks’ resistance and the amount of time the filament remains in the heated nozzle. This in‐depth study leads to optimum resolution to realize conductive tracks of 0.67 mm thickness and the first integration of fused deposition modeling (FDM)‐printed conductive traces with small‐outline integrated circuits to open a pathway for higher‐density 3D printed circuits. Finally, the transmission of digital data by a 3D printed circuit is demonstrated.

Progress in Glass-Ceramic Seal for Solid Oxide Fuel Cell Technology

Solid oxide fuel cells (SOFCs) have emerged as promising energy conversion devices nowadays. SOFC consists of several components such as cathode, anode, electrolyte, interconnects, and sealing materials. In planar SOFC stack construction, the sealant and interconnection functions play an important role. Glass and ceramics are quite popularly used as SOFC sealing materials to achieve several functions including preventing leakage of fuel and oxidants in the stack and electrically isolating cells in the stack. In this review, material preparation, material composition, ceramic properties especially thermal properties are compared from various systems that have been developed previously. The main challenges and complexities in the functional part of SOFC sealants include: (i) chemical incompatibility and instability in the oxidizing and reducing environment by adjusting the value of the thermal expansion coefficient (CTE) with the interconnecting material during SOFC operation, and (ii) insulation of oxidizing fuels and gases by matching CTE anode and cathode. Also, the sealant glass transition determines the maximum permissible working temperature of the SOFC. The choice of method and analysis will provide data on various ceramic attributes. The search for thermal attributes consisting of Glass transition (Tg), Deformation temp (Td), Crystallization temp (Tx), Melting pt (Tm) became a focus on SOFC sealant development.

High-Temperature Characterizations of a Half-Bridge Wire-Bondless SiC MOSFET Module

SiC MOSFET allows higher temperature capability with higher switching efficiency than that of conventional Si devices, due to its superior electrical and thermal properties. Nevertheless, there are few reports on the systematic characterization of the SiC MOSFET power module operating at high-temperature. In this paper, a SiC MOSFET power module with planar interconnection was designed and fabricated to achieve low parasitic inductance and improved thermal performance. The static and dynamic performance of the SiC power module were characterized at 200°C. The thermal resistance of the double-sided cooling power module is 28.5% lower than that of the one with single-sided cooling.

Deformable Interconnects with Embedded Devices in Flexible Fan-Out Packages

Abstract A new class of interconnects that exhibit resilience to mechanical deformation are demonstrated with flexible fan-out or embedded-die packages. Active device embedding in flexible substrates is accomplished with direct printed interconnects onto die pads. Such a planar fan-out interconnect technology with a low-cost manufacturable process-flow results in the lowest electrical parasitics compared to flipchip with adhesives or printed-ramp interconnections with surface-assembled devices. The interconnects are made with conductive flexible silver-elastomer composites to sustain elastic deformation. The process is also modified to realize flexible backside-assembled fan-out interconnections where the backside of the die is accessible.

Performance Evaluation of Centralized Reconfigurable Transmitting Power Scheme in Wireless Network-on-chip

Network-on-chip (NoC) is an on-chip communication network that allows parallel communication among all cores to improve inter-core performance. Wireless NoC (WiNoC) introduces long-range and high bandwidth radio frequency (RF) interconnects that can possibly reduce the multi-hop communication of the planar metal interconnects in conventional NoC platforms. In WiNoC, RF transceivers account for a significant power consumption, particularly its transmitter, out of its total communication energy. This paper evaluates the energy and latency performance of a closed loop power management mechanism which enables transmitting power reconfiguration in WiNoC based on number of erroneous received packets. The scheme achieves significant energy savings with limited performance degradation and insignificant impact on throughput.

Chip-on-Flex Packaging of Optoelectronic Devices in Polymer-Based Planar Optical Interconnects

A variety of applications in the use of optical and optoelectronic devices as well as their integrated circuits are increasingly penetrating into our daily routine. One of the most demanding fields is the sensing engineering. Meanwhile, the demand for more mechanical flexibility of systems and lower manufacturing budgets is continuously growing. Since the optical transparency is desired for coupling and transmission of optical signals, cost-effective transparent polymeric films are the promising candidates as carrier substrates. In this work, we aim to establish short-distance planar optical interconnects consisting of light sources/detectors and waveguides on the flexible transparent polymeric films for optical sensing functions. To achieve a miniaturized structure and ensure the flexibility of interconnects, bare chips of optoelectronic light sources/detectors are employed. Here, packaging of these chips carries the burden of all responsibilities in terms of ensuring the mechanical strength, electrical connection, thermal stability as well as the optical performance. It leads to the concept of chip-on-flex (CoF) packaging of optoelectronic devices. We present CoF packaging of a bare edge-emitting laser diode using the previously developed novel optodic bonding. While operating CoF packages, the optical performance of an active diode is strongly impaired by inefficient heat dissipation due to the extremely low thermal conductivity of employed polymeric films. Addressing this challenge, different concepts of thermomanagement are implemented. We elaborate the characterization results that evaluate the performance of CoF packages in terms of mechanical, electrical, thermo-optical, and opto-electronic properties. Two prototypes of planar optical interconnects are presented, with multi- and single-mode polymeric waveguide.

Substrate integrated waveguide interconnects in high-speed electronic systems

The big data era has arrived, and the requirements for high-speed data transmission continue to increase. It is urgent to develop new types of ultra high-speed and high-density interconnects to realize Terabit and even higher data transmission. Conventional planar interconnects such as microstrip lines, strip lines, and coplanar waveguides are in the form of open structures. Owing to the bandwidth and loss limitation, their signal integrity problems such as delays, attenuation, and crosstalk are severe and cannot transmit high-speed data when the data transmission rate is higher than a Gigabit. Based on conventional planar interconnects, SerDes (Serializer-Deserializer), differential lines, equalization, and pre-emphasis techniques were developed to improve the transmission performance. However, these techniques could not radically solve interconnect problems in high-speed data transmission. Substrate integrated waveguides (SIWs), as a new kind of planar interconnect, take advantage of the easy integration of conventional planar interconnects and the high bandwidth, low loss, and low crosstalk of waveguides. SIW interconnects have been gradually applied to realize high-speed data transmission. This paper presents all kinds of SIW interconnects, their physical structures, propagation performance, transmission modes and mechanisms, and data transmission rates in detail. Recent research studies of the authors are also introduced. According to the transmission mode, SIWs can be classified into three types: SIWs with TE mode, substrate integrated coaxial lines (SICLs) with TEM mode, and SIWs with mixed modes. The SIWs with TE mode have band-pass and hence base-band signals that should be modulated before transmission and demodulated after transmission. The introduction of modulation and demodulation techniques in SIWs increases the complexity of the transmission systems but can also improve the channel utilization and increase the data transmission rate. An SICL does not need modulation and demodulation since it propagates the TEM mode and has good signal integrity performance owing to its quasi-closed structure. SIWs with mixed modes integrate the SIW and other types of interconnects to simultaneously transmit TE mode and TEM mode by sharing conductors or media. According to the number of channels, SIWs can transmit single-channel signals through one physical channel, multichannel signals through one physical channel, or multichannel signals through multiple physical channels. Single-channel signal transmission through one physical channel uses one physical channel to transmit single-channel signals in single or multiple modes. Multichannel signal transmission through one physical channel uses one physical channel to transmit multichannel signals with complicated modulation techniques or multiple modes. Multichannel signal transmission through multiple physical channels uses multiple physical channels with single or multiple modes based on parallel data transmission. All kinds of new planar interconnects based on SIWs provide key techniques and solutions for high-speed data transmission.

Analytical Modeling and Performance Benchmarking of On-Chip Interconnects with Rough Surfaces

In planar on-chip copper interconnects, conductor losses due to surface roughness demands explicit consideration for accurate modeling of their performance metrics. This is quite pertinent for high-performance manycore processors/servers, where on-chip interconnects are increasingly emerging as one of the key performance bottlenecks. This paper presents a novel analytical model for parameter extraction in current and future on-chip interconnects. Our proposed model aids in analyzing the impact of spatial and vertical surface roughness on their electrical performance. Our analysis clearly depicts that as the technology nodes scale down; the effect of the surface roughness becomes dominant and cannot be ignored. Based on AFM images of fabricated ultra-thin copper sheets, we have extracted roughness parameters to define realistic surface profiles using the well-known Mandelbrot-Weierstrass (MW) fractal function. For our analysis, we have considered four current and future interconnect technology nodes (i.e., 45, 22, 13, 7 nm) and evaluated the impact of surface roughness on typical performance metrics, such as delay, energy, and bandwidth. Results obtained using our model are verified by comparing with industry standard field solver Ansys HFSS as well as available experimental data that exhibits accuracy within 9 percent. We present signal integrity analysis using the eye diagram at 1, 5, 10, and 18 Gbps bit rates to find the increase in frequency dependent losses due to surface roughness. Finally, simulating a standard three line on-chip interconnect structure, we also report the computational overhead incurred for different values of roughness and technology nodes.

(Invited) All-Carbon Interconnects - from 1D to 3D

Continuous downward scaling in silicon integrated circuit technology into the sub-20 nm regime has created critical challenges in chip manufacturing, among them, reliability and performance of on-chip interconnects. Current interconnect materials, Cu and W, face increased reliability challenges in the nanoscale as a result of electromigration failures at high current densities. Materials such as nanocarbons, metal silicides, and metallic nanowires are being considered as potential replacements for Cu and W. In particular, due to its superior electrical and mechanical properties as well as much higher current-carrying capacities, carbon nanotube (CNT) is a serious contender to replace Cu and W in on-chip interconnect via. However, the main challenge to functionalizing CNT vias is the metal-CNT contact resistance. To mitigate such challenge, a seamless three-dimensional all-carbon interconnect structure has been fabricated by growing CNTs directly on one or few layers of graphene (MLG). This 3D structure can potentially yield low resistance due to the strong C-C sp2 bonding in CNT and graphene and across the CNT-graphene interface. While such growth has been demonstrated, the CNT/graphene interfacial nanostructure and how it impacts the electrical properties of the 3D structure are far from being understood. Our test structure consists of MLG grown by annealing a Ni thin film in H2/CH4 ambient inside a low-pressure PECVD chamber, before being transferred onto an oxide-covered silicon substrate. Vertically aligned CNTs are then grown on the transferred MLG in a PECVD system using a similar recipe as in our previous work on CNT vias, resulting in a 3D all-carbon interconnect structure. Scanning and transmission electron microscopy images reveal CNT alignment and interfacial nanostructure comparable to the CNT-Cr interface in CNT via. The measured resistance of the 3D structure is compared with those of sub-100 nm linewidth CNT vias. Our results demonstrate the feasibility of fabricating a 3D CNT/graphene device, which can serve as the building block for all-carbon interconnects. Enhanced understanding of the relationship between interfacial nanostructure and device resistance can lead to eventual functionalization of contacts between CNT vias and a graphene-based planar interconnect network in the most advanced technology nodes.

Improved Reliability of Planar Power Interconnect With Ceramic-Based Structure

This paper proposes an advanced Si3N4 ceramic-based structure with through vias designed and filled with brazing alloy as a reliable interconnect solution in planar power modules. Finite-element (FE) modeling and simulation were first used to predict the potential of using the proposed Si3N4 ceramic-based structure to improve the heat dissipation and reliability of planar interconnects. Power cycling tests and nondestructive microstructural characterization were then performed on Si3N4 ceramic-based structures, flexible printed circuit boards (PCBs), and conventional Al wire interconnect samples to evaluate the FE predictions. Both the FE simulations and experimental tests were carried out on single Si diode samples where both the ceramic-based structures and flexible PCBs were bonded on the top sides of Si diodes with eutectic Sn-3.5Ag solder joints. The results obtained demonstrate that Si3N4 ceramic-based structures can significantly improve the reliability of planar interconnects. The experimental average lifetimes and FE simulated maximum creep strain accumulations for the ceramic-based structure and flexible PCB interconnect samples can reasonably be fitted to existing lifetime models for Sn-3.5Ag solder joints. Discrepancies between the models and experimental results can be attributed to defects and poor filling of the brazing alloy in the vias through the Si3N4 ceramic.

Analysis and Design of a 1200 V All-SiC Planar Interconnection Power Module for Next Generation More Electrical Aircraft Power Electronic Building Blocks

Compact, light weight and efficient Power Electronic Building Blocks are seen as fundamental components of future More Electric Power Systems, e.g. More Electrical Aircraft. Core elements supporting the trend are power modules employing solely SiC MOSFETs. In order to take advantage of the high switching speed enabled by SiC, novel modules concepts must be investigated. For example, low inductance planar interconnection technologies, integrated buffer capacitors and damping networks are possible solutions to mitigate switching overvoltages and oscillations at the switching node occurring for conventional modules. In this paper, the analysis and the design of a novel ultra-low inductance 1200 V SiC power module featuring an integrated buffer-damping network are discussed. The power module is first described and characterized with impedance measurements. Afterwards, a general optimization procedure for the sizing and the selection of the integrated components is presented and measurements are performed to verify the analysis and to highlight the improvements of the proposed solution.