Planar Interconnects Research Articles

Multilevel thin film packaging: applications and processes for high performance systems

IBM has developed and implemented multilayer thin films (MLTF) for both high end and cost-performance systems since the early 1980's. Copper-polymer and aluminum-polymer multilayer thin films have been implemented on silicon, alumina, and glass-ceramic substrates. The various MLTF implementations are: Two layers of Cu-polyimide interconnection on dry pressed alumina for single and dual chip applications, using wet etch of polyimide and subtractive etching of Cr-Cu-Cr for wiring. One to two layers of planar Cu-polyimide interconnection on alumina and glass-ceramic multichip modules for redistribution of chip I/O's to the ceramic vias, using laser ablation for via definition, subtractive etching of Cr-Cu-Cr for wiring definition, and liftoff for bonding pad definition. Four layers of Al-polyimide multichip interconnection on silicon substrates, using reactive ion etching for via definition, subtractive etching of aluminum for wiring definition, and evaporation through a mask for bonding pad definition. Four to five layers of planar Cu-polyimide interconnection on glass-ceramic substrates, using laser ablation for via definition, photosensitive polyimide (PSPI) lithography and blanket electroplating for wiring definition, and liftoff for bonding pad definition. Four or five layers of non-planar Cu-polyimide interconnection on alumina, silicon, and glass-ceramic substrates, using laser ablation or photosensitive polyimide lithography for via definition, additive electroplating or subtractive etching of Cu for wiring definition, and additive electroplating for bonding pad definition. In this paper we discuss the evolution of these thin film technologies as well as the process choices, their merits, and the reasoning behind the various choices. >

Optical perfect-shuffle interconnection using a computer-generated hologram

We propose the use of a computer-generated hologram that combines a fanout and focusing element that can be used to perform an optical perfect-shuffle interconnection. The hologram is designed by calculation of the interference fringes between diverging waves from four point sources and a reference plane wave. With this element we show experimentally the resulting perfect-shuffle pattern. The use of the computer-generated hologram makes it easy to implement a planar optical perfect-shuffle interconnect, which is compact, has low aberration, and is easy to align. The planar optics configuration for a perfect-shuffle interconnection network is also discussed.

Polymer waveguides: characterization through prism–film coupler method

Cr(VI) and Fe(III) doped polyvinyl alcohol) and poly(acrylic acid) polymers have been used as real-time holographic recording media as well as materials to fabricate planar waveguides. Planar wave guides were made of these metal ion doped polymer thin films. Changes in the absorption spectra of these polymer films due to irradiation with an intense illumination of 468 nm light were observed. Modifications in optical properties of dichromated poly(vinyl alcohol) (DCPVA), dichromated poly(acrylic acid) (DCPAA), and ferric chloride doped polyvinyl alcohol) (FePVA) were experimentally determined by the prism–film coupler (PFC) method for the first time. Changes in the refractive index at 632.8 nm were monitored for different exposure energies. Modification of the modal properties was observed and the refractive index of these films was also determined from the angular position of the guided modes. Optical losses in both exposed and unexposed films of DCPVA, DCPAA, and FePVA were measured employing a coupling set-up with two prisms. Observed results suggest that these materials can find successful applications in promising areas like integrated optics and planar optical interconnects.

Holographic interconnects: transverse Bragg waveguides

We propose a new type of planar optical interconnect, the transverse Bragg waveguide. With this interconnect, We propose a new type light distribution is converted into a one-dimensional output light distribution by means one-dimensional input of holographic patterning along the direction of propagation.

An electromigration model that includes the effects of microstructure and temperature on mass transport

A model for electromigration in thin metal film interconnects is presented that includes two components of diffusion. The grain-boundary and lattice components of mass transport are considered in terms of their temperature dependence and the metallurgical ‘‘structure’’ of patterned planar interconnects. Interconnect structure is defined in terms of single- and polycrystalline line segments, which result from the local grain microstructure for a patterned interconnect line. The dependence of the diffusional flux on the length and type of line segment is included in the model. The results indicate that the grain structure of the film plays an important role in determining the relative contribution of the diffusion components to mass transport. The model assumes that the length and type of interconnect line segment determines the relative contribution of grain boundary and lattice diffusion components, and provides a means for extrapolating accelerated test results for planar interconnects by taking into consideration the temperature dependence of the diffusion mechanisms, and the effect of the local microstructure on diffusion. The model also indicates that extrapolations made using Black’s equation may result in an overestimate of safe operating conditions. Calculations show that the effective activation energy depends on the median grain size and its distribution parameter, D50 and σ, respectively, and the interconnect linewidth W. Model calculations of electromigration lifetime t50 were compared to experimental results obtained on patterned interconnects using sputter-deposited Al-1.5% Cu alloy films. The experimental data support a linewidth-dependent electromigration activation energy and show that the dependence of t50 on linewidth for W≤3D50 results from a change in the dominant diffusion mechanism with temperature, linewidth, and local interconnect ‘‘structure.’’

Fabrication of hybrid diffractive optics for fiber interconnects

The fabrication and performance of a hybrid diffractive optical system for use in planar optic interconnects is presented. Specifically, a novel fiber-optic tap utilizing both lithographic surface relief microlenses and interferometrically generated holographic volume elements is discussed. This system serves as an interface between fiber and planar optic interconnects for signal distribution. Design tradeoffs and experimental results are given. >

Planar optical implementation of crossover interconnects

We propose a planar optical configuration for implementation of crossover interconnects. The planar overlay allows two-dimensional pixel arrays located on a wafer-scale integrated circuit to be interconnected in a compact and vibrationally robust configuration. By using an acute-angle microprism array with apex angles of 70.52 deg fabricated on a silicon substrate, we show the experimental result of the crossover interconnections. Some practical limits of the planar optical crossover interconnections are also discussed.

Design and analysis of fixed planar holographic interconnects for optical neural networks

A neural-network architecture of multifaceted planar interconnection holograms and optoelectronic neurons is analyzed. Various computer-generated hologram techniques are analyzed and tested for their ability to produce an interconnection hologram with high-accuracy interconnects and high diffraction efficiency. A new technique is developed by using the Gerchberg-Saxton algorithm, followed by a random-search error minimization that produces the highest interconnect accuracy and the highest diffraction efficiency of the techniques tested. Analysis of the system shows that the hologram has the capacity to connect 5000 neuron outputs to 5000 neuron inputs with bipolar synapses and that the encoded synaptic weights have an accuracy of ~5 bits. A simple feedback system is constructed and demonstrated.

Diffraction-limited blazed reflection diffractive microlenses for oblique incidence fabricated by electron-beam lithography

Blazed reflection diffractive microlenses potentially have many uses. The fabrication accuracy and the optical characteristics of these microlenses can be greatly improved compared with transmission diffractive microlenses. The reflection microlenses for oblique incidence can be flexibly used without a beam splitter. The functions of the electron-beam writing system that we developed have been expanded so that the diffraction-limited microlenses for oblique incidence can be fabricated. It is demonstrated that the fabricated microlens exhibits diffraction-limited focusing characteristics with 78% high efficiency at a large oblique angle of 30 degrees . These microlenses could be used as key devices in planar optics and optical interconnections.

Influence of Two‐Level Planar Interconnection Processes Using Bias‐Sputtered SiO2 for MOSFETs

The influence of two‐level planar interconnection using bias‐sputtered for MOSFETs has been investigated. The degradation of static characteristics due to both the deposition and two‐level interconnection was small, and was reduced to a negligibly small amount by annealing at 450°C in a ambient for 30 min. However, the influence on long‐term reliability, i.e., hot‐carrier immunity, was not negligible and could not be removed by annealing. The origins of the long‐term reliability degradation in the two‐level planar interconnection were attributed to, primarily, the bias sputter deposition step and, secondarily, the dry etching step for via holes. It was possible to reduce the degradation due to the bias sputter deposition step to the same degree as that of the via hole dry etching step by raising the deposition temperature.

CVD-W deposition and dry etch processes for planarized metallizations and tungsten interconnect techniques

Abstract An improved W deposition process was developed using H 2 reduction of WF 6 . In a cold wall reactor at a higher pressure (12 mbar) and at higher flows of WF 6 the step coverage was sufficient to fill up contact holes with an aspect ratio of 2. A low pressure etch back process using SF 6 /O 2 was developed, which shows no local-loading effect and produces co-planar W plugs with no W residues on topographical features. The feasibility of some planarization schemes was demonstrated.

An advanced single-level polysilicon submicrometer BiCMOS technology

An advanced VLSI (very large scale integration) technology providing high-performance n-p-n bipolar (f/sub T/=9 GHz) and submicrometer gate-length MOS (metal-oxide-semiconductor) transistors is described. This technology is intended for high-speed logic circuits operating at 5 V, where a high level of circuit integration and low power consumption is required. Features include vertical n-p-n transistors with walled, self-aligned polysilicon emitters and lightly doped extrinsic base (LDEB) extensions MOS transistors feature complementary-doped polysilicon gates and LDD (lightly doped drain) structures for both NMOS and PMOS. Optional buried contacts between the polysilicon layer and all junctions in the silicon substrate are provided. Polysilicon emitters, MOS gates, base/collector, and source/drain regions are silicided. In addition, a fully planarized metal interconnect scheme incorporating nonselective CVD (chemical-vapor-deposited) tungsten and vertical-walled contacts and vias is utilized. >

A heat resistant PIQ, polymer‐based interconnection using a multilevel lift‐off pillar fabrication

AbstractTo achieve a planar multilevel interconnection, we have developed a process using an improved lift‐off pillar fabrication technique in conjunction with a new kind of heat resistant polymer, a copolyimide‐isoindoloquinazolinedione polymer (PIQ). As spin‐on dielectric layer, the PIQ polyimide is shown to satisfy both the processing criteria and interconnection criteria (high thermal resistance, good planarization properties and excellent dielectric properties).

A New LSI Interconnection Method for IC Cards

A new LSI interconnection method, the printed wiring connection (PWC) method, has already been developed. This method involves a planar interconnection, formed by screen printing, utilizing a polymeric conductor. Using this new method, an IC card was made, and the feasibility of applying this method to IC card packaging was investigated. The IC card developed has passed most reliability tests based on the ISO standard and several environmental tests to prove its application feasibility.

Fine pattern technology for multilevel metallization with piq insulation

AbstractPIQ (patented) is known to be a very effective polymer for use in planar multilevel interconnection technology. To realize fine patterns and a high order of integration of this technology, we studied a wet‐etching mechanism with an etchant based on hydrazine hydrate. Hydrazine hydrate is known to be an etchant for the PIQ, as are also NaOH and KOH. However, hydrazine hydrate is not suitable for fine‐pattern technology because it causes a region of swelling in PIQ film. We analyzed the swelling region by infrared spectroscopy and found that ethylenediamine solves the swelling quite effectively. Based on these results, we developed a new etchant containing hydrazine hydrate and ethylenediamine. The new etchant enables the creation of stable 3 μ2 via‐holes in the PIQ film. The electrical properties of these holes are also found to be quite good.

An Anodic Process for Forming Planar Interconnection Metallization for Multilevel LSI

Anodic processing has been extended to aluminum alloy metallurgy. A procedure for forming completely planar interconnection metallization has been described. The factors which control line profile and the electrical isolation of closely spaced conductors have been investigated, and the conclusions used to define the anodizing conditions. The planar structure and the increased cross‐sectional area of the conductor which result from the use of this process make increased circuit density possible.

Multilayer Metallization with Planar Interconnect Structure Utilizing CVD Al2 O 3 Film

A new, multilayer metallization system has been developed for the purpose of fabricating a planar interconnect structure. This system comprises two levels of metal interconnection, and the first‐level metal layer is buried in a low temperature CVD film pyrolytically deposited by at 420°C. The metal chosen for both layers is aluminum, and the insulator is phosphosilicate glass. In the metal processing, a self‐aligned photolithographic technique is applied in which positive photoresist AZ‐1350 plays an important role in forming the first‐level Al layer and the film.

Planar multi-layer interconnect structure : H. Tsunemitsu and H. Shiba. NEC Res. Dev. Japan, No. 25, April (1972), p. 74

Planar multi-layer interconnect structure : H. Tsunemitsu and H. Shiba. NEC Res. Dev. Japan, No. 25, April (1972), p. 74