Planar Gate Research Articles

Methodology for Characterizing Degradation Locations of Planar and Trench Gate SiC Power Mosfets Under Repetitive Short-Circuit Stress

Methodology for Characterizing Degradation Locations of Planar and Trench Gate SiC Power Mosfets Under Repetitive Short-Circuit Stress

Study of the Bias Driven Threshold Voltage Drift of 1.2 kV SiC MOSFETs in Power Cycling and High Temperature Gate Bias Tests

Threshold voltage instability remains a challenging aspect for metal-oxide semiconductor-field-effect-transistors (MOSFETs) made from silicon carbide (SiC). SiC MOSFETs from two manufacturers, with planar and trench gate structure respectively, have been tested under different test procedures, including power cycling and high temperature gate bias tests. The standard power cycling test setup has been modified to enable an in situ threshold voltage read-out procedure with the hysteresis method. The recorded threshold voltage drift has been compared with results from high temperature gate bias tests applying a simple power law fit, with the intention to predict the drift in power cycling tests. For the group with trench MOSFETs comparable results between power cycling and gate stress tests have been achieved.

A semi-cellular Z-type Gate SOI-LDMOS with Improved Gate Control Capability

A Semi-cellular Z-type Gate SOI-LDMOS (ZG LDMOS) with Improved Gate Control Capability is proposed, and its physical mechanism is studied by SENTAURUS. It is a semi-cellular structure similar to "Z" consisting of a Trench Gate (TG) and a Planar Gate (PG). At the on-state, the inversion layer of the conductive channel is not only formed at the top of the P-well region, but also formed along the side wall of the Z Gate, expanding the width of the channel, improving the electron injection ability and reducing the specific on-resistance (Ron,sp). In addition, the Z Gate can also form a uniform current distribution from the drift region to the bottom, which is helpful to reduce the Ron,sp, improve the transconductance and enhance the current control ability. The 3D simulation results show that BV, Ron,sp are 187.3 V and 4.45 mΩ cm2, respectively. The FOM reached 7.91 MW/cm2. Compared with the conventional LDMOS, the FOM value of ZG LDMOS increased by 58.8 %, which breaks through the silicon limit of RESURF.

A nanoscale photonic thermal transistor for sub-second heat flow switching

Control of heat flow is critical for thermal logic devices and thermal management and has been explored theoretically. However, experimental progress on active control of heat flow has been limited. Here, we describe a nanoscale radiative thermal transistor that comprises of a hot source and a cold drain (both are ~250 nm-thick silicon nitride membranes), which are analogous to the source and drain electrodes of a transistor. The source and drain are in close proximity to a vanadium oxide (VOx)-based planar gate electrode, whose dielectric properties can be adjusted by changing its temperature. We demonstrate that when the gate is located close ( < ~1 µm) to the source-drain device and undergoes a metal-insulator transition, the radiative heat transfer between the source and drain can be changed by a factor of three. More importantly, our nanomembrane-based thermal transistor features fast switching times ( ~ 500 ms as opposed to minutes for past three-terminal thermal transistors) due to its small thermal mass. Our experiments are supported by detailed calculations that highlight the mechanism of thermal modulation. We anticipate that the advances reported here will open new opportunities for designing thermal circuits or thermal logic devices for advanced thermal management.

H/O edge passivated B/N co-doped armchair graphene nanoribbon field-effect transistors, based on first principles

This study employs the nonequilibrium Green’s function method in conjunction with density functional theory to fabricate and analyze a Graphene Nanoribbon Field-Effect Transistor (GNRFET). The co-doping of B and N creates built-in electric fields, thereby reducing leakage current. The results demonstrate effective control performance of planar gates, as evidenced by an increase in IDS with rising gate voltage. Furthermore, a negative differential conductance phenomenon is observed at bias voltages exceeding 0.7 V, exhibiting correlation with transmission spectra and energy band structures. To precisely illustrate the electron distribution within the doped scattering region, calculations involving transport paths, the molecular projection self-consistent Hamiltonian (MPSH), and the emission eigenvalues and eigenstates of the device are conducted. This research provides a reference for exploring and developing smaller and more energy-efficient AGNR field effect transistor designs and implementations. The principal objective of this paper is to investigate the potential applications of these smaller, more energy-efficient devices.

Numerical Calculation of Static Strength Performance of Planar Gate Structures

As an important part of the ecological environment, rivers provide an important guarantee for the production and life in China. At present, domestic and foreign for the construction of the gate has been gradually shaped, hydraulic steel gate gradually developed as a hydroelectric power station high head, flood discharge flow of large gate type, the smooth opening and closing of the gate is related to the entire water conservancy hub and downstream of the safety of the residents' lives. For the safety of plane gate, this paper adopts Ansys software to establish a finite element model of plane gate, and calculates the most dangerous point stress of plane gate by considering its most unfavourable loading condition. At the same time, the service life of the allowable stress reduction was considered. The analysis results show that the planar gate meets the strength safety. The main beam is simplified into slender beam and thin-walled deep beam, and the calculation formula of slender beam in the mechanics of materials and thin-walled deep beam in the literature is used to calculate the positive bending stress in the mid-span cross-section of the main beam of the gate, and a comparative analysis is carried out with the results of Ansys, which shows that the positive bending stress in the mid-span cross-section of the main beam obtained by simplifying the main beam into a thin-walled deep beam is more close to the results of Ansys calculation. The results of this paper provide an important reference for the structural strength analysis of planar gates.

Actively controlled anode auxiliary gate super-junction insulated gate bipolar transistor with extremely low

When dealing with the super-junction insulated gate bipolar transistor (SJ-IGBT), due to its unipolar/bipolar mixed conduction mechanism, the approaches to improve its – are not exactly the same as for non-SJ IGBTs. In the pursuit of extremely low , a planar auxiliary anode gate SJ-IGBT (AAG-SJ-IGBT) is proposed based on a 650 V SJ-IGBT to realize a unipolar turn-off as observed in SJ-MOSFETs accompanied by fast switching and extremely low . The planar auxiliary anode gate provides similar effects but better feasibility than conventional trench ones. Sentaurus TCAD simulation results for the proposed AAG-SJ-IGBT indicate a 69% smaller and a 54% lower than the FP-SJ-IGBT, and its – is significantly optimized from cathode-improved SJ-IGBTs. The analysis of carrier and current density reveals the static and dynamic characteristics of the AAG-SJ-IGBT and the principle for excellent – trade-off.

Investigation of the time dependent gate dielectric stability in SiC MOSFETs with planar and trench gate structures

In this work, the time-dependent dielectric breakdown (TDDB) analysis is performed to understand the gate oxide reliability in SiC MOSFETs with two different structures, i.e., planar and trench gate structures. We have discovered different gate leakage current behaviors between the SiC MOSFETs with planar gate (Sample A) and trench gate (Sample B) during the forward gate bias stress. Notably, the slight increase of the gate current during the stress and the negative activation energy (Ea = −0.07 eV) observed in Sample A suggest that the hole generation caused by the impact ionization can be occurred during the forward gate TDDB tests. Furthermore, the SiC MOSFETs with trench gate structure (Sample B) exhibit the operation voltage of 55.7 V (exponential law) and 57.3 V (power law) for the 0.001 % failure of 30 years under 175 °C, indicating that SiC trench gate MOSFETs with enough thick gate dielectric (87.1 nm (bottom) and 77.9 nm (sidewall)) can have the promising forward gate TDDB stability.

Different reverse leakage current transport mechanisms of planar Schottky barrier diodes(SBDs) on sapphire and GaN substrate

The effects of different substrates on the off-state leakage current in gallium nitride (GaN) planar diodes are experimentally demonstrated and studied by analyzing temperature-dependent current–voltage characteristics. The two devices exhibit different leakage mechanisms despite being subjected to the same process conditions. The device with a sapphire substrate shows a more intricate leakage mechanism, implying the presence of additional leakage channels compared to the device with free-standing substrates. The electrical leakage characteristics in the planar GaN-on-sapphire device (referred to as utemp-SBD) and GaN substrate device (referred to as usub-SBD) Schottky barrier diodes (SBD) can be described by two distinct processes as the reverse bias gradually increases: utemp-SBD go through the thermionic emission (TE), variable range hopping (VRH), Frenkel–Poole (FP) emission and space-charge-limited conduction (SCLC) model; The leakage conduction mechanism of usub-SBD include TE, VRH, and FP emission mechanisms. It is noteworthy that in device 1, there is a rapid increase in leakage current within the voltage range of −36 to −40 V, primarily driven by the SCLC mechanism. This effect arises due to the presence of intrinsic traps in GaN grown on a heterogeneous substrate. Additionally, in the voltage range of −7 to −50 V (348 K to 448 K), the leakage mechanism shifts from FP emission to the VRH model, possibly due to variations in the Schottky barrier height.This study provides an in-depth analysis of the leakage mechanisms observed on different substrates and offers valuable insights for the design of planar gate transistors to minimize or avoid the occurrence of leakage channels.

High-Energy Proton and Atmospheric-Neutron Irradiations of SiC Power MOSFETs: SEB Study and Impact on Channel and Drift Resistances

Accelerated single event burnout (SEB) tests with 200 MeV protons and atmospheric-neutrons were performed for commercial SiC power MOSFETs with different architectures ( <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">i.e</i> ., planar gate, asymmetric trench and symmetric trench). The average electric fields over the depletion layer width and the electric field distributions are reported for the tested conditions and compared for the three architectures, confirming the necessity of a lower de-rating for the trench design to protect from SEB, compared to planar ones. In addition to the epitaxial layer design, the influence of other design parameters on the SEB threshold is discussed. Finally, to investigate the presence of precursor damage in the pre-SEB region, a methodology is presented and used to study the radiation-induced degradation of the channel and drift resistances of devices which survived the SEB tests.

Influence of Gate Geometry on the Characteristics of AlGaN/GaN Nanochannel HEMTs for High-Linearity Applications.

In this study, AlGaN/GaN nanochannel high-electron-mobility transistors (HEMTs) with tri-gate (TGN-devices) and dual-gate (DGN-devices) structures were fabricated and investigated. It was found that the peak value of the transconductance (Gm), current gain cut-off frequency (fT) and power gain cut-off frequency (fmax) of the TGN-devices were larger than that of the DGN-devices because of the enhanced gate control from the top gate. Although the TGN-devices and DGN-devices demonstrated flattened transconductance, fT and fmax profiles, the first and second transconductance derivatives of the DGN-devices were lower than those of the TGN-devices, implying an improvement in linearity. With the nanochannel width decreased, the peak value of the transconductance and the first and second transconductance derivatives increased, implying the predominant influence of sidewall gate capacitance on the transconductance and linearity. The comparison of gate capacitance for the TGN-devices and DGN-devices revealed that the gate capacitance of the tri-gate structure was not simply a linear superposition of the top planar gate capacitance and sidewall gate capacitance of the dual-gate structure, which could be attributed to the difference in the depletion region shape for tri-gate and dual-gate structures.

Experimental Comparison of a New 1.2 kV 4H-SiC Split-Gate MOSFET with Conventional SiC MOSFETs in Terms of Reliability Robustness

In this paper, we compare a new 1.2 kV rated 4H-SiC split-gate (SG) MOSFET with the conventional planar-gate (PG) MOSFETs. Both structures were fabricated with the same design rules and process platform. Therefore, the structures have similar electrical parameters, such as ON-state drain-source resistance (RON), breakdown voltage (BV), threshold voltage (Vth), and body diode forward voltage (VSD). It is shown that the Ciss/Coss/Crss capacitances of the SG-MOSFET can be reduced by 7%/8%/17%, respectively, compared with PG-MOSFET. It is also shown that the SG-MOSFET has the potential to reduce switching losses without compromising the static performance. Moreover, it maintains the robustness of the device, and an optimized layout design with spaced holes in the gate poly is adopted. Therefore, there is no obvious degradation between the SG-MOSFET and the PG-MOSFET in terms of avalanche and short-circuit endurance capabilities.

Comparison of the Performance-Degrading Near-Interface Traps in Commercial SiC MOSFETs

This paper presents a comparison of the density of performance-degrading near-interface traps (NITs) in the most commonly available 1200 V commercial N-channel SiC power metal–oxide–semiconductor field-effect transistors (MOSFETs). A recently developed integrated-charge technique was used to measure the density of NITs with energy levels aligned to the conduction band, which degrade MOSFET’s performance by capturing and releasing electrons from the channel biased in the strong-inversion condition. Trench MOSFETs of one manufacturer have lower densities of these NITs in comparison to MOSFETs with the planar gate structure, corresponding to observed higher channel-carrier mobility in trench MOSFETs. Different response-time distributions were also observed, corresponding to different spatial location of the measured NITs.

Simulation study on dynamic characteristics of SiC MOSFET

In this paper, the third generation power MOSFET is introduced, and the physical model based on silicon based MOSFET is improved for SiC MOSFET, and the commercial planar gate and trench gate 1.2kV SiC MOSFET are simulated. The accuracy of physical modals is tested by comparing the static characteristics with commercial ones. The dynamic characteristics of two MOSFETs are simulated by inductively clamped double pulse circuit, and the circuit parameters are analyzed according to the static characteristics of the devices. The switching loss of the two MOSFETs is calculated and compared by using TCAD software. In the two devices with the same volume, the trench gate structure has the larger switching loss.

Total Ionizing Dose Effects of 60Co γ-Ray Radiation on Split-Gate SiC MOSFETs

SiC power devices require resistance to both single-event effects (SEEs) and total ionizing dose effects (TIDs) in a space radiation environment. The split-gate-enhanced VDMOSFET (SGE-VDMOSFET) process can effectively enhance the radiation resistance of SiC VDMOS, but it has a certain impact on the gate oxide reliability of SiC VDMOS. This paper investigates the impact mechanism and regularity of using the SGE process to determine the radiation resistance and long-term reliability of SiC VDMOS under other identical processes and radiation conditions. Our experimental results show that after 60Co γ-ray irradiation, the degradation degrees of the static parameters of SGE-VDMOSFET and planar gate VDMOSFET (PG-VDMOSFET) are similar. The use of the new process leads to more defects in the oxide layer, reducing the long-term reliability of the device, but its stability can recover after high-temperature (HT) accelerated annealing. This research indicates that enhancing the resistance of SEEs using an SGE-VDMOSFET structure requires simultaneously considering the demand for TIDs and long-term reliability.

Simulation Studies on Single-Event Effects and the Mechanisms of SiC VDMOS from a Structural Perspective.

The single-event effect reliability issue is one of the most critical concerns in the context of space applications for SiC VDMOS. In this paper, the SEE characteristics and mechanisms of the proposed deep trench gate superjunction (DTSJ), conventional trench gate superjunction (CTSJ), conventional trench gate (CT), and conventional planar gate (CT) SiC VDMOS are comprehensively analyzed and simulated. Extensive simulations demonstrate the maximum SET current peaks of DTSJ-, CTSJ-, CT-, and CP SiC VDMOS, which are 188 mA, 218 mA, 242 mA, and 255 mA, with a bias voltage VDS of 300 V and LET = 120 MeV·cm2/mg, respectively. The total charges of DTSJ-, CTSJ-, CT-, and CP SiC VDMOS collected at the drain are 320 pC, 1100 pC, 885 pC, and 567 pC, respectively. A definition and calculation of the charge enhancement factor (CEF) are proposed. The CEF values of DTSJ-, CTSJ-, CT-, and CP SiC VDMOS are 43, 160, 117, and 55, respectively. Compared with CTSJ-, CT-, and CP SiC VDMOS, the total charge and CEF of the DTSJ SiC VDMOS are reduced by 70.9%, 62.4%, 43.6% and 73.1%, 63.2%, and 21.8%, respectively. The maximum SET lattice temperature of the DTSJ SiC VDMOS is less than 2823 K under the wide operating conditions of a drain bias voltage VDS ranging from 100 V to 1100 V and a LET value ranging from 1 MeV·cm2/mg to 120 MeV·cm2/mg, while the maximum SET lattice temperatures of the other three SiC VDMOS significantly exceed 3100 K. The SEGR LET thresholds of DTSJ-, CTSJ-, CT-, and CP SiC VDMOS are approximately 100 MeV·cm2/mg, 15 MeV·cm2/mg, 15 MeV·cm2/mg, and 60 MeV·cm2/mg, respectively, while the value of VDS = 1100 V.

Considerations for SiC super junction MOSFET: On-resistance, gate structure, and oxide shield

SiC super junction (SJ-) MOSFETs have recently gained attention due to their potentially low on-resistance (RON). In this paper, we conduct TCAD numerical simulations to study SiC non-SJ-MOSFETs, planar-gate (P-) SJ-MOSFETs, and trench-gate (T-) SJ-MOSFETs with voltage levels ranging from 1.5 kV to 15 kV. We focus on the design considerations for SiC SJ-MOSFETs, including on-resistance, gate structure, and oxide shield. Our results reveal that SiC SJ-MOSFETs are suitable for higher voltage level applications (5.5 kV or beyond), unlike non-SJ-MOSFETs, which exhibit extremely high increasing drift resistance with voltage level. The simulations suggest that the T-SJ-MOSFET achieves lower RON than the P-SJ-MOSFET, mainly due to the narrower p/n pillar in the trench structure, rather than higher channel density. Additionally, it is necessary to fabricate a p-shield in the T-SJ-MOSFET to reduce the oxide field and increase the switching speed. While the gate structure (planar gate or trench gate) has been a focused research topic for non-SJ-MOSFETs, our study highlights the importance of considering the gate structure for SJ-MOSFET design as well.

Planar Multi-Gate Artificial Synaptic Transistor with Solution-Processed AlOx Solid Electric Double Layer Dielectric and InOx Channel

Multi-terminal artificial synaptic devices are promising for building neural morphological networks and manufacturing neural chips. In this study, planar multi-gate InOx-based artificial synaptic transistor was demonstrated by using solution-processed AlOx as an electric double layer (EDL) dielectric with mobile hydrogen protons. The excitatory postsynaptic current (EPSC) was successfully controlled by adjusting amplitude, duration, and interval of the stimulating voltage pulses applied on the planar gates. The EPSC stimulated by multiple inputs shows the property of sublinear summation. As spatial resolution function of the artificial synaptic transistor, the EPSC depends on the presynaptic (planar gate) area and distance to the channel, nonlinearly. The paired-pulse facilitation (PPF), depending on time sequence, demonstrates the temporal resolution function of the multi-gate artificial synaptic transistor. The study shows the potential of planar multi-gate AlOx/InOx EDL transistor as multi-terminal artificial synaptic device.

Au Nanoparticles/HfO₂/Fully Depleted Silicon-on-Insulator MOSFET Enabled Rapid Detection of Zeptomole COVID-19 Gene With Electrostatic Enrichment Process

In this work, a novel sensing structure based on Au nanoparticles/HfO2/fully depleted silicon-on-insulator (AuNPs/HfO2/FDSOI) MOSFET is fabricated. Using such a planar double gate MOSFET, the electrostatic enrichment (ESE) process is proposed for the ultrasensitive and rapid detection of the coronavirus disease 2019 (COVID-19) ORF1ab gene. The back-gate (BG) bias can induce the required electric field that enables the ESE process in the testing liquid analyte with indirect contact with the top-Si layer. It is revealed that the ESE process can rapidly and effectively accumulate ORF1ab genes close to the HfO2 surface, which can significantly change the MOSFET threshold voltage ([Formula: see text]). The proposed MOSFET successfully demonstrates the detection of zeptomole (zM) COVID-19 ORF1ab gene with an ultralow detection limit down to 67 zM (~0.04 copy/[Formula: see text]) for a test time of less than 15 min even in a high ionic-strength solution. Besides, the quantitative dependence of [Formula: see text] variation on COVID-19 ORF1ab gene concentration from 200 zM to 100 femtomole is also revealed, which is further confirmed by TCAD simulation.

4H-SiC Trench Gate Lateral MOSFET With Dual Source Trenches for Improved Performance and Reliability

The SiC trench gate lateral MOSFET featuring dual source trenches is proposed in this work. 2D numerical simulations by TCAD are conducted to study the performance and the reliability of the proposed structure and the conventional ones. With the trench gate, the device specific ON-resistance is reduced by more than 50% compared to that of the planar gate device. The device with proposed dual source trenches can also prevent the Pwell punch through problem that occurs in conventional lateral LMOS. As a result, a blocking voltage over 1200V can be achieved with the proposed structure. The proposed devices have two types of configurations. Compared with the configuration of double shallow trenches, the configuration of deep and shallow trenches can mitigate the curvature effect near the P+ source region by increasing the effective curvature radius. As a result, the RESURF doping and epi thickness windows are both expanded by <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$1.5{\times }$ </tex-math></inline-formula> . Furthermore, as the deep source trenches push the electric field away from the gate trench, the off-state oxide field is effectively reduced to below 3MV/cm. Thus, the long-term reliability is substantially improved. In addition, the deep and shallow source trench configuration provides the enhanced screen effect and hence lowers the gate charge by 50%. Faster switching can be achieved with this structure.