Parallel Pixel Research Articles

A real-time, power-efficient architecture for mean-shift image segmentation

Image segmentation is essential to image processing because it provides a solution to the task of separating the objects in an image from the background and from each other, which is an important step in object recognition, tracking, and other high-level image-processing applications. By partitioning the input image into smaller regions, segmentation performs the balancing act of extracting the main areas of interest (objects and important features) that further help to interpret the image, while remaining immune to irrelevant noise and less important background scenes. Image-segmentation applications branch off into a plethora of domains, from decision-making applications in computer vision to medical imaging and quality control to name just a few. The mean-shift algorithm provides a unique unsupervised clustering solution to image segmentation, and it has an established record of good performance for a wide variety of input images. However, mean-shift segmentation exhibits an unfavorable computational complexity of $$O(kN^2)$$ , where $$N$$ represents the number of pixels and $$k$$ the number of iterations. As a result of this complexity, unsupervised image segmentation has had limited impact in autonomous applications, where a low-power, real-time solution is required. We propose a novel hardware architecture that exploits the customizable computing power of FPGAs and reduces the execution time by clustering pixels in parallel while meeting the low-power demands of embedded applications. The architecture performance is compared with existing CPU and GPU implementations to demonstrate its advantages in terms of both execution time and energy.

A digitally driven pixel circuit with current compensation for AMOLED microdisplays

A novel digitally driven pixel circuit for active-matrix organic light-emitting diode (OLED) microdisplays is proposed and evaluated. This circuit supports both pulse width modulation and pulse density modulation digital drive approaches. Only three transistors and one capacitor are required per pixel for the proposed circuit. A current mirror is used to compensate for the pixel current changes that occur because of the degradation of the OLEDs over time. The compensation current depends on the potential of the common cathode, the properties of the current mirror, and the Width/Length (W/L) ratio of the drive transistor. The proposed digital pixel circuit also has advantages in circuit layout compared with analog pixel circuits.

Fuzzy filtering method for color videos corrupted by additive noise.

A novel method for the denoising of color videos corrupted by additive noise is presented in this paper. The proposed technique consists of three principal filtering steps: spatial, spatiotemporal, and spatial postprocessing. In contrast to other state-of-the-art algorithms, during the first spatial step, the eight gradient values in different directions for pixels located in the vicinity of a central pixel as well as the R, G, and B channel correlation between the analogous pixels in different color bands are taken into account. These gradient values give the information about the level of contamination then the designed fuzzy rules are used to preserve the image features (textures, edges, sharpness, chromatic properties, etc.). In the second step, two neighboring video frames are processed together. Possible local motions between neighboring frames are estimated using block matching procedure in eight directions to perform interframe filtering. In the final step, the edges and smoothed regions in a current frame are distinguished for final postprocessing filtering. Numerous simulation results confirm that this novel 3D fuzzy method performs better than other state-of-the-art techniques in terms of objective criteria (PSNR, MAE, NCD, and SSIM) as well as subjective perception via the human vision system in the different color videos.

VLSI implementation of high‐throughput parallel H.264/AVC baseline intra‐predictor

This study presents a parallel very large scale integrated circuits architecture for an intra-predictor based on a fast 4 × 4 algorithm. For real-time scheduling, the proposed algorithm overcomes the data dependency between intra-prediction and intra-coding, thereby improving coding performance and reducing the number of coding cycles. The high-speed architecture for intra-prediction includes configurable computation cores to process YUV components using 10 pixel parallelism. Prediction for one macro-block (MB) coding (luminance: 4 × 4 and 16 × 16 block modes; chrominance: 8 × 8 block modes) can all be completed within 256 cycles. The proposed architecture achieves throughput of 410 kMB/s, suitable for 1920 × 1080/35 Hz 4:2:0 HDTV encoder at a working frequency of 105 MHz.

Pixel front-end development in 65 nm CMOS technology

Luminosity upgrade of the LHC (HL-LHC) imposes severe constraints on the detector tracking systems in terms of radiationhardness and capability to cope with higher hit rates. One possibleway of keeping track with increasing luminosity is the usage of moreadvanced technologies. Ultra deep sub-micron CMOS technologies allow adesign of complex and high speed electronics with high integrationdensity. In addition, these technologies are inherently radiationhard. We present a prototype of analog pixel front-end integratedcircuit designed in 65 nm CMOS technology with applications orientedtowards the ATLAS Pixel Detector upgrade. The aspects of ultra deepsub-micron design and performance of the analog pixel front-endcircuits will be discussed.

A new digital readout integrated circuit (DROIC) with pixel parallel A/D conversion and reduced quantization noise

This paper represents a novel digital readout for infrared focal plane arrays with 2.33Ge− charge handling capacity while achieving quantization noise of 161e−. Pixel level A/D conversion has been realized by pulse frequency modulation (PFM) technique supported with a novel method utilizing extended integration that eliminates the requirement for an additional column ADC. Digital pixel operates with two phases; the first phase is as ordinary PFM in charge domain and the second phase is in time domain, allowing the fine quantization and low quantization noise. A 32×32 prototype has been manufactured and tested. Measured peak SNR at half well fill is 71dB with significant SNR improvement for low illuminated pixels due to extremely low quantization noise. 32×32 ROIC dissipates only 1.1mW and the figure of merit for power dissipation is measured to be 465 fJ/LSB, compared to 930 fJ/LSB and 1470 fJ/LSB of the state of the art.

개선된 보팅 정책을 적용한 허프 변환 하드웨어 구조

The Hough transform for line detection is widely used in many machine vision applications due to its robustness against data loss and distortion. However, it is not appropriate for real-time embedded vision systems, because it has inefficient computation structure and demands a large number of memory accesses. Thus, this paper proposes an improved voting scheme of the Hough transform, and then applies this scheme to a Hough transform hardware architecture so that it can provide real-time performance with less hardware resource. The proposed voting scheme reduces computation overhead of the voting procedure using correlation between adjacent pixels, and improves computational efficiency by increasing reusability of vote values. The proposed hardware architecture, which adopts this improved scheme, maximizes its throughput by computing and storing vote values for many adjacent pixels in parallel. This parallelization for throughput improvement is accomplished with little hardware overhead compared with sequential computation.

Scalable Programmable Motion Effects on GPUs

AbstractWe present an efficient and scalable system that enables programmable motion effects on GPUs. Our system is based on the framework proposed by Schmid et al. [SSBG10] that extends the concept of a surface shader to that of a programmable motion effect. While capable of expressing a variety of motion depiction styles, the execution of motion effect programs requires global knowledge about all portions of an object's surface that passes in front of a pixel during an arbitrarily long period of time, resulting in extremely high memory usage and significantly restricting the degree of parallelism of typical GPU rendering algorithms that parallelize computations over pixels in each frame of animations. To address this problem, we design our system to process multiple frames of a pixel in parallel. This new parallelization approach enables better utilization of GPU memory and also makes it possible to design an efficient out‐of‐core algorithm required in rendering real‐world animations. We also develop an analytical visibility algorithm to resolve depth conflicts of objects, reducing the required temporal resampling rate and further exposing parallelism. Experiments show that we are able to handle very large scenes and improve runtime performance up to an order of magnitude.

Optimal scan strategy for mega-pixel and kilo-gray-level OLED-on-silicon microdisplay

The digital pixel driving scheme makes the organic light-emitting diode (OLED) microdisplays more immune to the pixel luminance variations and simplifies the circuit architecture and design flow compared to the analog pixel driving scheme. Additionally, it is easily applied in full digital systems. However, the data bottleneck becomes a notable problem as the number of pixels and gray levels grow dramatically. This paper will discuss the digital driving ability to achieve kilogray-levels for megapixel displays. The optimal scan strategy is proposed for creating ultra high gray levels and increasing light efficiency and contrast ratio. Two correction schemes are discussed to improve the gray level linearity. A 1280×1024×3 OLED-on-silicon microdisplay, with 4096 gray levels, is designed based on the optimal scan strategy. The circuit driver is integrated in the silicon backplane chip in the 0.35 μm 3.3 V-6 V dual voltage one polysilicon layer, four metal layers (1P4M) complementary metal-oxide semiconductor (CMOS) process with custom top metal. The design aspects of the optimal scan controller are also discussed. The test results show the gray level linearity of the correction schemes for the optimal scan strategy is acceptable by the human eye.

First results from the characterization of a three-dimensional deep N-well MAPS prototype for vertexing applications

The prototype of a three-dimensional (3D) monolithic active pixel sensor (MAPS) has been characterized. The device, featuring a 20μm pitch, was designed based on the same approach that was adopted in developing the so-called deep N-well (DNW) MAPS in planar CMOS process. The new 3D design relies upon stacking two homogeneous tiers fabricated in a 130nm CMOS technology. Different kinds of test structures, including single pixels, 3×3 arrays and 8×8 and 16×16 matrices were tested. Functionality of the collecting deep N-well electrode, the analog front-end and the digital readout electronics has been demonstrated. Inter-tier communication was found to work properly in the case of redundant interconnection and could be exploited for the test of the analog pixel section. On the other hand, inter-tier interconnections based on individual bond pads were proven ineffective likely due to wafer misalignment.

Ion beam analysis based on cellular nonlinear networks

Abstract. The development of a non- destructive measurement method for ion beam parameters has been treated in various projects. Although results are promising, the high complexity of beam dynamics has made it impossible to implement a real time process control up to now. In this paper we will propose analysing methods based on the dynamics of Cellular Nonlinear Networks (CNN) that can be implemented on pixel parallel CNN based architectures and yield satisfying results even at low resolutions.

Design of Analog Pixel Memory for Low Power Application in TFT-LCDs

Two types of analog memory cells realized in a 3-μm low temperature polycrystalline silicon (LTPS) technology are proposed to achieve low power application for thin film transistor liquid crystal displays (TFT-LCDs). By employing the inversion signal in the storage capacitor with complementary source follower, the frame rate to refresh the static image can be reduced from 60 to 3.16 Hz with the output decay less than 0.1 V under the input data from 1 to 4 V. To further diminish threshold voltage drop from source follower structure, a compensation technique is implemented to the proposed analog memory cells. In addition, asymmetric output voltage can be also minimized by adding a reference voltage to achieve symmetric output waveform.

X-ray analog pixel array detector for single synchrotron bunch time-resolved imaging

Dynamic X-ray studies can reach temporal resolutions limited by only the X-ray pulse duration if the detector is fast enough to segregate synchrotron pulses. An analog integrating pixel array detector with in-pixel storage and temporal resolution of around 150 ns, sufficient to isolate pulses, is presented. Analog integration minimizes count-rate limitations and in-pixel storage captures successive pulses. Fundamental tests of noise and linearity as well as high-speed laser measurements are shown. The detector resolved individual bunch trains at the Cornell High Energy Synchrotron Source at levels of up to 3.7 × 10(3) X-rays per pixel per train. When applied to turn-by-turn X-ray beam characterization, single-shot intensity measurements were made with a repeatability of 0.4% and horizontal oscillations of the positron cloud were detected.

A Graphics Parallel Memory Organization Exploiting Request Correlations

Real-time graphics applications require memory organizations featuring parallel pixel access and low-cost implementation. This work bases on a nonlinear skew mapping scheme and exploits the correlation between consecutive requests for pixels to design an efficient parallel memory organization. The mapping achieves parallel access, of mn pixels in various shapes, to the memory organized with mn banks. The proposed design technique combines the mapping properties and the spatial correlations among pixel requests to eliminate conflicts by spending at most one extra cycle every mn consecutive parallel pixel accesses. Consequently, the technique ensures that any pixel pattern-among these commonly used in graphics-can be accessed in a single cycle from any image location. The address computations become straightforward as the numbers of the requested pixels and the banks-apart from equal-can be powers of 2.

P‐40: Design of Analog Pixel Memory Circuit with Low Temperature Polycrystalline Silicon TFTs for Low Power Application

AbstractA new analog pixel memory cell realized in a 3‐μm LTPS technology is proposed to achieve low‐power consumption for TFT‐LCDs. By employing the inversion data in storage capacitor with complementary source follower, the frame rate to refresh the static image can be reduced from 60Hz to 3Hz with output decay only less than 0.075V under the input data from 1V to 4V.

A new phase for two-photon microscopy

A new phase for two-photon microscopy

Focal-Plane Algorithmically-Multiplying CMOS Computational Image Sensor

The CMOS image sensor computes two-dimensional convolution of video frames with a programmable digital kernel of up to 8 times 8 pixels in parallel directly on the focal plane. Three operations, a temporal difference, a multiplication and an accumulation are performed for each pixel readout. A dual-memory pixel stores two video frames. Selective pixel output sampling controlled by binary kernel coefficients implements binary-analog multiplication. Cross-pixel column-parallel bit-level accumulation and frame differencing are implemented by switched-capacitor integrators. Binary-weighted summation and concurrent quantization is performed by a bank of column-parallel multiplying analog-to-digital converters (MADCs). A simple digital adder performs row-wise accumulation during ADC readout. A 128 times 128 active pixel array integrated with a bank of 128 MADCs was fabricated in a 0.35 mum standard CMOS technology. The 4.4 mm times 2.9 mm prototype is experimentally validated in discrete wavelet transform (DWT) video compression and frame differencing.

A 140-MHz 94 K Gates HD1080p 30-Frames/s Intra-Only Profile H.264 Encoder

This paper presents a HD1080p 30-frames/s H.264 intra encoder operated at 140 MHz with just 94 K gate count and 0.72-mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> core area for digital video recorder or digital still camera applications. To achieve high throughput and low area cost for high-definition video, we apply the modified three-step fast intra prediction technique to reduce the cycle count while keeping the quality as close as full search. Then, in architecture scheduling, we further adopt the variable pixel parallelism instead of constant four-pixel parallelism to speed up performance on the critical intra prediction part while keeping other parts unchanged for low area cost. The achieved design only needs half of the working frequency and reduces the gate count cost by 23.5% compared with the previous design with the same HD720p 30-frames/s requirement. Besides, our design at 140 MHz can support HD1080p 30 frames/s for digital video encoder or 4096 times2304 images with 6.78 frames/s for digital still camera application.

A new ATLAS pixel front-end IC for upgraded LHC luminosity

A new pixel Front-End (FE) IC is being developed in a 130 nm technology for use in the upgraded ATLAS pixel detector. The new pixel FE will be made of smaller pixels (50×250 μm vs. 50×400 μm for the present FE, FE-I3), a much improved active area over inactive area ratio, and a new analog pixel chain tuned for low power and new detector input capacitance. The higher luminosity for which this IC is tuned implies a complete redefinition of the digital architecture logic, which will not be based on End-of-Column data buffering but on local pixel logic and local pixel data storage. An overview of the new FE is given with particular emphasis on the new digital logic architecture and possible architecture variations.

A high-speed area detector for novel imaging techniques in a scanning transmission electron microscope

A scanning transmission electron microscope (STEM) produces a convergent beam electron diffraction pattern at each position of a raster scan with a focused electron beam, but recording this information poses major challenges for gathering and storing such large data sets in a timely manner and with sufficient dynamic range. To investigate the crystalline structure of materials, a 16×16 analog pixel array detector (PAD) is used to replace the traditional detectors and retain the diffraction information at every STEM raster position. The PAD, unlike a charge-coupled device (CCD) or photomultiplier tube (PMT), directly images 120–200 keV electrons with relatively little radiation damage, exhibits no afterglow and limits crosstalk between adjacent pixels. Traditional STEM imaging modes can still be performed by the PAD with a 1.1 kHz frame rate, which allows post-acquisition control over imaging conditions and enables novel imaging techniques based on the retained crystalline information. Techniques for rapid, semi-automatic crystal grain segmentation with sub-nanometer resolution are described using cross-correlation, sub-region integration, and other post-processing methods.