Parallel Pixel Research Articles

A high-speed area detector for novel imaging techniques in a scanning transmission electron microscope

A scanning transmission electron microscope (STEM) produces a convergent beam electron diffraction pattern at each position of a raster scan with a focused electron beam, but recording this information poses major challenges for gathering and storing such large data sets in a timely manner and with sufficient dynamic range. To investigate the crystalline structure of materials, a 16×16 analog pixel array detector (PAD) is used to replace the traditional detectors and retain the diffraction information at every STEM raster position. The PAD, unlike a charge-coupled device (CCD) or photomultiplier tube (PMT), directly images 120–200 keV electrons with relatively little radiation damage, exhibits no afterglow and limits crosstalk between adjacent pixels. Traditional STEM imaging modes can still be performed by the PAD with a 1.1 kHz frame rate, which allows post-acquisition control over imaging conditions and enables novel imaging techniques based on the retained crystalline information. Techniques for rapid, semi-automatic crystal grain segmentation with sub-nanometer resolution are described using cross-correlation, sub-region integration, and other post-processing methods.

Fast retinal vessel tree extraction: A pixel parallel approach

AbstractEarly ocular disease diagnosis is an important field in medical research. From the image processing point of view, many strategies and algorithms have been developed to deal with the extraction of the retinal vessel tree. Although reliable and accurate results have been obtained, the main disadvantage in most of these proposals is the high computation effort required. In this paper, a methodology to extract the retinal vessel tree has been developed and tested in a fine‐grain pixel‐parallel processor array. An analysis of the execution time has been made to demonstrate its capabilities regarding the computation speed. Moreover, an analysis of the accuracy using a publicly available database has been made to validate the algorithm performance. Copyright © 2008 John Wiley & Sons, Ltd.

Compact and Power-Efficient Implementation of Rank-Order Filters Using Time-Domain Digital Computation Technique

A compact and power-efficient digital implementation of rank-order filters compatible with focal-plane image processing has been developed based on a time-domain computation technique. The magnitude of analog pixel intensity is represented as a pulse width in the pulse width modulation scheme, and the rank-order filtering is accomplished using simple digital adders and a binary counter. As a result, a very compact implementation comparable to analog counterparts has been achieved, while preserving the accuracy and programmability of digital implementation. This will enable us to use the rank-order filter as a building block in a parallel processing array. A test chip capable of performing multiple rank-order filtering for up to 16 inputs was designed and fabricated in a 0.35 µm standard complementary metal oxide semiconductor (CMOS) technology. Experimental results have demonstrated the correct operation of the circuit in low-power dissipation of 0.44 mW at 3.3 V with a very compact core size of 0.014 mm2. In addition, the circuit has shown the speed performance of over 260 k ranks/s at 8-bit resolution, which is more than sufficient for use at typical video frame rates.

Amorphous <inline-formula><math display="inline" overflow="scroll"><mrow><mi>TiAl</mi></mrow></math></inline-formula> films for micromirror arrays with stable analog deflection integrated on complementary metal oxide semiconductors

Large micromechanical mirror arrays (MMA) with analog pixel deflection integrated onto active CMOS address circuitry require both high-quality planar reflective optical surfaces and a stable deflection versus voltage characteristic. However, for implementing a CMOS-compatible surface-micromachining process, certain obstacles such as a restricted thermal budget and a limited selection of suitable materials must be overcome. Amorphous TiAl is presented as a new actuator material for monolithical MEMS integration onto CMOS circuitry. TiAl films may be sputter deposited at room temperature, have an x-ray amorphous structure, and a low stress gradient. The glassy structure and high melting point make TiAl less vulnerable to stress relaxation, which makes TiAl an ideal spring material. One-level actuators with TiAl or Al-TiAl-Al structural layers and two-level actuators with separate TiAl spring and Al-alloy mirror layers were fabricated and tested with respect to their drift stability. The stability of TiAl-based actuators was found to be superior in comparison to one-level Al-alloy actuators. Two-level actuators with TiAl hinges emerge as the most promising design.

Column-Parallel Vision Chip Architecture for High-Resolution Line-of-Sight Detection Including Saccade

Although the line-of-sight (LoS) is expected to be useful as input methodology for computer systems, the application area of the conventional LoS detection system composed of video camera and image processor is restricted in the specialized area, such as academic research, due to its large size and high cost. There is a rapid eye motion, so called 'saccade' in our eye motion, which is expected to be useful for various applications. Because of the saccade's very high speed, it is impossible to track the saccade without using high speed camera. The authors have been proposing the high speed vision chip for LoS detection including saccade based on the pixel parallel processing architecture, however, its resolution is very low for the large size of its pixel. In this paper, we propose and discuss an architecture of the vision chip for LoS detection including saccade based on column-parallel processing manner for increasing the resolution with keeping high processing speed.

A 144<formula formulatype="inline"><tex>$\,\times\,$</tex></formula>144 Current-Mode Image Sensor With Self-Adapting Mismatch Reduction

We present a novel CMOS continuous-current imager that uses nonvolatile floating-gate charge storage in each pixel for automatic cancellation of fixed-pattern noise (FPN) and vignetting artifacts. We demonstrate the ability to reduce image artifacts over a wide range of incident light intensities. Adaptation occurs for each pixel in parallel, using a unique pixel circuit that employs hot-electron injection in stable feedback to accurately match a reference value. The adaptation mechanism stores a reference image, which may be uniform for FPN cancellation or nonuniform for various imaging applications. The design has been fabricated in a commercially available 3-metal, 2-poly 0.5-mum standard CMOS technology. Experimental results confirm the ability to reduce the FPN variance by a factor of 178x at the intensity at which adaptation was performed, and by a factor of 34x over five orders of magnitude of intensity. Adaptation takes as little as 4 s and the 144 times 144 image can be acquired at 0.9 frames/s. During normal operation, the chip consumes 140 muW under standard office lighting conditions at room temperature.

Imaging with the invisible light

We describe a UV photodetector with single photon (electron) counting and imaging capability. It is based on a CsI photocathode, a GEM charge multiplier and a self-triggering CMOS analog pixel chip with 105 k pixels at 50 μm pitch. The single photoelectron produced by the absorption of a UV photon is drifted to and multiplied inside a single GEM hole. The coordinates of the GEM avalanche are reconstructed with high accuracy (4 μm rms) by the pixel chip. As a result the map of the GEM holes, arranged on a triangular pattern at 50 μm pitch, is finely imaged.

Evolution of Ultra-High-Speed CCD Imagers

This paper reviews the high-speed video cameras developed by the authors. A video camera operating at 4,500 frames per second (fps) was developed in 1991. The partial and parallel readout scheme combined with fully digital memory with overwriting function enabled the world fastest imaging at the time. The basic configuration of the camera later became a de facto standard of high-speed video cameras. A video camera mounting an innovative image sensor achieved 1,000,000 fps in 2001. In-situ storage with more than 100 CCD memory elements is installed in each pixel of the sensor, which is capable of recording image signals in all pixels in parallel. Therefore, the sensor was named ISIS, the in-situ storage image sensor. The ultimate parallel recording operation promises the theoretical maximum frame rate. A sequence of more than one hundred consecutive images reproduces a smoothly moving image at 10 fps for more than 10 seconds. Currently, an image sensor with ultrahigh sensitivity is being developed in addition to the ultra-high frame rate, named PC-ISIS, the photon-counting ISIS, for microscopic biological observation. Some other technologies supporting the ultra-high-speed imaging developed are also presented.

High speed optically sectioned fluorescence lifetime imaging permits study of live cell signaling events

We present a time domain optically sectioned fluorescence lifetime imaging (FLIM) microscope developed for high-speed live cell imaging. This single photon excited system combines wide field parallel pixel detection with confocal sectioning utilizing spinning Nipkow disc microscopy. It can acquire fluorescence lifetime images of live cells at up to 10 frames per second (fps), permitting high-speed FLIM of cell dynamics and protein interactions with potential for high throughput cell imaging and screening applications. We demonstrate the application of this FLIM microscope to real-time monitoring of changes in lipid order in cell membranes following cholesterol depletion using cyclodextrin and to the activation of the small GTP-ase Ras in live cells using FRET.

Demodulation Pixel Based on Static Drift Fields

A novel pixel architecture for two-dimensional pixel parallel demodulation of modulated light waves is introduced, enabling real-time three-dimensional (3-D) imaging. Applications for such methods can be found in the field of surveillance, robotics, automotive, and industry security applications. The pixel architecture is based on large areas of static drift fields and relatively small demodulation regions. The large area of static drift field forms the basic photodetection region. The constant drift field enables the very fast transport of photo-generated charges to the sampling region where demodulation of the light signal is performed. The main advantages compared to recently used demodulation pixels are lower power consumption and higher optical fill factor or sensitivity. The first implementation is a pixel of 40times40 mum <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> size with 25% optical fill factor. Measurements prove the concept of transporting photo-generated charges within less than 1 ns to the demodulation node. The applicability of the pixel in 3-D imaging applications is highlighted by distance measurements achieving millimeter distance resolution

Vision Chip Architecture for Detecting Line of Sight Including Saccade

Rapid eye motion, or so called saccade, is a very quick eye motion which always occurs regardless of our intention. Although the line of sight (LOS) with saccade tracking is expected to be used for a new type of computer-human interface, it is impossible to track it using the conventional video camera, because of its speed which is often up to 600 degrees per second. Vision Chip is an intelligent image sensor which has the photo receptor and the image processing circuitry on a single chip, which can process the acquired image information by keeping its spatial parallelism. It has also the ability of implementing the very compact integrated vision system. In this paper, we describe the vision chip architecture which has the capability of detecting the line of sight from infrared eye image, with the processing speed supporting the saccade tracking. The vision chip described here has the pixel parallel processing architecture, with the node automata for each pixel as image processing. The acquired image is digitized to two flags indicating the Purkinje's image and the pupil by comparators at first. The digitized images are then shrunk, followed by several steps of expanding by node automata located at each pixel. The shrinking process is kept executed until all the pixels disappear, and the pixel disappearing at last indicates the center of the Purkinje's image and the pupil. This disappearing step is detected by the projection circuitry in pixel circuit for fast operation, and the coordinates of the center of the Purkinje's image and the pupil are generated by the simple encoders. We describe the whole architecture of this vision chip, as well as the pixel architecture. We also describe the evaluation of proposed algorithm with numerical simulation, as well as processing speed using FPGA, and improvement in resolution using column parallel architecture.

Thresholding algorithm for local and parallel processing

AbstractIn this paper, we propose a thresholding algorithm. This algorithm works under a severe constraint: each pixel in a processed image must be derived from only information of its neighboring pixels. This constraint is very important for a low‐cost device such as a mobile camera, because it makes it possible to process each pixel in parallel. The proposed algorithm deals with gray‐scale images, and determines the threshold based on edge information. The proposed algorithm is represented by local and parallel image processing and has been tested using 104 scenery images. The result shows that the proposed algorithm can binarize images. © 2006 Wiley Periodicals, Inc. Electr Eng Jpn, 157(2): 50–56, 2006; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/eej.20267

A pixel ionization chamber used as beam monitor at the Institut Curie—Centre de Protontherapie de Orsay (CPO)

The Dipartimento di Fisica Sperimentale and the Istituto Nazionale di Fisica Nucleare (INFN), Torino, in collaboration with the Institut Curie—Centre de Protontherapie de Orsay (CPO), have developed and built a pixel parallel plate ionization chamber to be used as monitor for the proton therapy beam line at the Institut Curie—CPO (Orsay, France). The sensitive area of the detector is (160×160) mm 2, with the anode segmented in 1024 square pixels arranged in a 32×32 matrix; the area of each pixel is (5×5) mm 2. The detector has been placed on the beam line just upstream of the last collimator to monitor the beam shape and to measure the stability and reproducibility of the delivery system. In this paper, we present a detailed description of the detector and the results of a set of preliminary tests.

局所並列処理のための二値化アルゴリズム

In this paper, we propose a thresholding algorithm. This algorithm works under a severe constraint: each pixel in a processed image must be derived from only information of its neighboring pixels. This constraint is very important for a low-cost device such as a mobile camera, because it makes it possible to process each pixel in parallel. The proposed algorithm deals with gray-scale images, and determines the threshold based on edge information. The proposed algorithm is represented by local and parallel image processing and has been tested using 104 scenery images. The result shows that the proposed algorithm can binarize images. © 2006 Wiley Periodicals, Inc. Electr Eng Jpn, 157(2): 50–56, 2006; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/eej.20267

Seeded region growing: an extensive and comparative study

Seeded region growing (SRG) algorithm is very attractive for semantic image segmentation by involving high-level knowledge of image components in the seed selection procedure. However, the SRG algorithm also suffers from the problems of pixel sorting orders for labeling and automatic seed selection. An obvious way to improve the SRG algorithm is to provide more effective pixel labeling technique and automate the process of seed selection. To provide such a framework, we design an automatic SRG algorithm, along with a boundary-oriented parallel pixel labeling technique and an automatic seed selection method. Moreover, a seed tracking algorithm is proposed for automatic moving object extraction. The region seeds, which are located inside the temporal change mask, are selected for generating the regions of moving objects. Experimental evaluation shows good performances of our technique on a relatively large variety of images without the need of adjusting parameters.

A radiation-tolerant electronic readout system for portal imaging

A new electronic portal imaging device, EPID, is under development at the Karolinska Institutet and the Royal Institute of Technology. Due to considerable demands on radiation tolerance in the radiotherapy environment, a dedicated electronic readout system has been designed. The most interesting aspect of the readout system is that it allows to read out ∼1000 pixels in parallel, with all electronics placed outside the radiation beam—making the detector more radiation resistant. In this work we are presenting the function of a small prototype (6×100 pixels) of the electronic readout board that has been tested. Tests were made with continuous X-rays (10–60 keV) and with α particles. The results show that, without using an optimised gas mixture and with an early prototype only, the electronic readout system still works very well.

Character Region Extraction Algorithm from Scenery Images by Local and Parallel Processing

In this paper, we propose an algorithm extracting character domains from scenery images. This algorithm works under a severe constraint: each pixel in a processed image must be derived from only information of the neighboring pixels. This constraint is very important for a low cost device such as a mobile camera, because it makes possible to process each pixel in parallel. The proposed algorithm deals with color information based on physiological knowledge, and uses size of regions for judging whether a region is characters or not. The proposed algorithm is represented by local and parallel image processing and has been tested using 100 scenery images. The result shows that the proposed algorithm can extract character regions in a rate of more than 90%.

High-speed wide-field coherence-gated imaging via photorefractive holography with photorefractive multiple quantum well devices

The parallel pixel acquisition inherent in wide-field coherence-gated imaging techniques offers the possibility of high-frame-rate imaging and volumetric imaging, including through scattering media. We discuss photorefractive holography using sensitive, dynamic photorefractive multiple quantum well (PRQW) films as a promising approach and, after reviewing the factors that determine the sensitivity of this technique, we demonstrate that high-frame-rate wide-field coherence gated imaging is possible at 830 frames per second with PRQW devices using a non-intensified camera to record the diffracted signal.

A pixel-level automatic calibration circuit scheme for capacitive fingerprint sensor LSIs

We propose a pixel-level automatic calibration circuit scheme that initializes a capacitive fingerprint sensor LSI to eliminate the influence of the surface condition, which is degraded by dirt during long-time use. The scheme consists of an automatic calibration circuit for each pixel and a calibration control circuit for the pixel array. The calibration is executed by adjusting variable capacitance in each pixel to make the sensor signals of all pixels the same. The calibration control circuit selects the pixels in parallel, and calibrates all pixels in a short time. The scheme was applied to a fingerprint sensor LSI using the 0.5-/spl mu/m CMOS process/sensor process, and clear fingerprint images were obtained even for a degraded surface condition. This confirms that the scheme is effective for capturing consistent clear images during long-time use.

Analog front-end cell designed in a commercial 0.25 /spl mu/m process for the ATLAS pixel detector at LHC

A new analog pixel front-end cell has been developed for the ATLAS detector at the future Large Hadron Collider (LHC) at the European Laboratory for Particle Physics (CERN). This analog cell has been submitted in two commercial 0.25 /spl mu/m CMOS processes (in an analog test chip format), using special layout techniques for radiation hardness purposes. It is composed of two cascaded amplifiers followed by a fast discriminator featuring a detection threshold within the range of 1000 to 10000 electrons. The first preamplifier has the principal role of providing a large bandwidth, low input impedance, and fast rise time in order to enhance the time-walk and crosstalk performance, whereas the second fully differential amplifier is aimed at delivering a sufficiently high-voltage gain for optimum comparison. A new do feedback concept renders the cell tolerant of sensor leakage current up to 300 nA and provides monitoring of this current. Two 5-bit digital-to-analog converters tolerant to single-event upset have been implemented for threshold and recovery-time pixel-to-pixel matching purposes. Special attention has been paid to the power-supply rejection ratio to minimize sensitivity to pickup. The complete cell dissipates 30 /spl mu/W, occupies an area of 50/spl times/90 /spl mu/m/sup 2/ and is operated with a single 1.6-V power supply. Measurements of two test chips are presented.