Pipelined Architecture Research Articles

Looped Pipelines Enabling Effective 3D Qubit Lattices in a Strictly 2D Device

A proposed pipelining architecture processes a stack of qubit arrays and implements an effective 3D qubit lattice on a physical 2D hardware substrate, allowing the realization of a variety of code structures with the cost of magic state distillation reduced by 2 orders of magnitude.

Removal of artifact in bio signal using ECG for QRS detection

This paper proposed a removal of artifacts in bio signal, which is used to improve the signal strength by using Pan Tompkins algorithm for QRS signal detection. This algorithm is compared with different filtering technique such as noise cancellation filter, squaring filter, moving average and differentiator filter. Recorded bio signal and SNR ratio measurement will be shown in simulation result using MATLAB 2018a software tool, this filtering technique data contains noisy input signal with 3 second time delay. The sampling rate of the ECG signal is 200Hz on power line noise from machine power supply, ECG signal wandering after cancellation DC drift and normalization process. Efficacy of the filters for removing the artifact and generate the effect on the ECG waveform, in terms of accuracy rate, the SNR ratio of ECG in pipeline architecture has 93% of efficiency is achieved.

A high frame-rate of cell-based histogram-oriented gradients human detector architecture implemented in field programmable gate arrays

In respect of the accuracy, one of the well-known techniques for human detection is the histogram-oriented gradients (HOG) method. Unfortunately, the HOG feature calculation is highly complex and computationally intensive. Thus, in this research, we aim to achieve a resource-efficient and low-power HOG hardware architecture while maintaining its high frame-rate performance for real-time processing. A hardware architecture for human detection in 2D images using simplified HOG algorithm was introduced in this paper. To increase the frame-rate, we simplify the HOG computation while maintaining the detection quality. In the hardware architecture, we design a cell-based processing method instead of a window-based method. Moreover, 64 parallel and pipeline architectures were used to increase the processing speed. Our pipeline architecture can significantly reduce memory bandwidth and avoid any external memory utilization. an altera field programmable gate arrays (FPGA) E2-115 was employed to evaluate the design. The evaluation results show that our design achieves performance up to 86.51 frame rate per second (Fps) with a relatively low operating frequency (27 MHz). It consumes 48,360 logic elements (LEs) and 4,363 registers. The performance test results reveal that the proposed solution exhibits a trade-off between Fps, clock frequency, the use of registers, and Fps-to-clock ratio.

Designing a Performance-Centric MAC Unit with Pipelined Architecture for DNN Accelerators

Designing a Performance-Centric MAC Unit with Pipelined Architecture for DNN Accelerators

A Hybrid Approach for Efficient and Secure Point Multiplication on Binary Edwards Curves

The focus of this article is to present a novel crypto-accelerator architecture for a resource-constrained embedded system that utilizes elliptic curve cryptography (ECC). The architecture is built around Binary Edwards curves (BEC) to provide resistance against simple power analysis (SPA) attacks. Furthermore, the proposed architecture incorporates several optimizations to achieve efficient hardware resource utilization for the point multiplication process over GF(2m). This includes the use of a Montgomery radix-2 multiplier and the projective coordinate hybrid algorithm (combination of Montgomery ladder and double and add algorithm) for scalar multiplication. A two-stage pipelined architecture is employed to enhance throughput. The design is modeled in Verilog HDL and verified using Vivado and ISE design suites from Xilinx. The obtained results demonstrate that the proposed BEC accelerator offers significant performance improvements compared to existing solutions. The obtained throughput over area ratio for GF(2233) on Virtex-4, Virtex-5, Virtex-6, and Virtex-7 Xilinx FPGAs are 9.43, 14.39, 26.14, and 28.79, respectively. The computation time required for a single point multiplication operation on the Virtex-7 device is 19.61 µs. These findings indicate that the proposed architecture has the potential to address the challenges posed by resource-constrained embedded systems that require high throughput and efficient use of available resources.

MiniGraph: Querying Big Graphs with a Single Machine

This paper presents MiniGraph, an out-of-core system for querying big graphs with a single machine. As opposed to previous single-machine graph systems, MiniGraph proposes a pipelined architecture to overlap I/O and CPU operations, and improves multi-core parallelism. It also introduces a hybrid model to support both vertex-centric and graph-centric parallel computations, to simplify parallel graph programming, speed up beyond-neighborhood computations, and parallelize computations within each subgraph. The model induces a two-level parallel execution model to explore both inter-subgraph and intra-subgraph parallelism. Moreover, MiniGraph develops new optimization techniques under its architecture. Using real-life graphs of different types, we show that MiniGraph is up to 76.1x faster than prior out-of-core systems, and performs better than some multi-machine systems that use up to 12 machines.

A Highly Pipelined and Highly Parallel VLSI Architecture of CABAC Encoder for UHDTV Applications.

Recently, specifically designed video codecs have been preferred due to the expansion of video data in Internet of Things (IoT) devices. Context Adaptive Binary Arithmetic Coding (CABAC) is the entropy coding module widely used in recent video coding standards such as HEVC/H.265 and VVC/H.266. CABAC is a well known throughput bottleneck due to its strong data dependencies. Because the required context model of the current bin often depends on the results of the previous bin, the context model cannot be prefetched early enough and then results in pipeline stalls. To solve this problem, we propose a prediction-based context model prefetching strategy, effectively eliminating the clock consumption of the contextual model for accessing data in memory. Moreover, we offer multi-result context model update (MCMU) to reduce the critical path delay of context model updates in multi-bin/clock architecture. Furthermore, we apply pre-range update and pre-renormalize techniques to reduce the multiplex BAE's route delay due to the incomplete reliance on the encoding process. Moreover, to further speed up the processing, we propose to process four regular and several bypass bins in parallel with a variable bypass bin incorporation (VBBI) technique. Finally, a quad-loop cache is developed to improve the compatibility of data interactions between the entropy encoder and other video encoder modules. As a result, the pipeline architecture based on the context model prefetching strategy can remove up to 45.66% of the coding time due to stalls of the regular bin, and the parallel architecture can also save 29.25% of the coding time due to model update on average under the condition that the Quantization Parameter (QP) is equal to 22. At the same time, the throughput of our proposed parallel architecture can reach 2191 Mbin/s, which is sufficient to meet the requirements of 8 K Ultra High Definition Television (UHDTV). Additionally, the hardware efficiency (Mbins/s per k gates) of the proposed architecture is higher than that of existing advanced pipeline and parallel architectures.

Architecting the Autocuckoo Filter to Defend Against Cross-Core Cache Attacks

Cross-core cache timing side-channel attacks, which observe cache access behavior of victims running on different physical cores to infer sensitive information, have become a significant threat. Although the attacks are covert, they cause the attacked cachelines to frequently migrate among cache hierarchies, rendering abnormal traffic. Based on this observation, the proposed scheme PiPoMonitor records cache-memory access traffic and prefetch suspicious lines under attack to interfere with adversaries’ probes. In pursuit of security and performance, PiPoMonitor exploits a Cuckoo filter as the recording structure and introduces two features to it: 1) autonomic deletion and 2) relocation accelerating. The former exponentially increases the uncertainty of record eviction against reverse engineering attacks, while the latter leverages a pipelined architecture to alleviate the impact of intensive filter queries on the memory critical path. PiPoMonitor is not only able to effectively mitigate cross-core cache attacks and defeat sophisticated defense-aware attackers but also induces a negligible performance penalty and acceptable hardware overhead.

List-serial pipelined hardware architecture for SCL decoding of polar codes

For polar codes, the performance of successive cancellation list (SCL) decoding is capable of approaching that of maximum likelihood decoding. However, the existing hardware architectures for the SCL decoding suffer from high hardware complexity due to calculating L decoding paths simultaneously, which are unfriendly to the devices with limited logical resources, such as field programmable gate arrays (FPGAs). In this paper, we propose a list-serial pipelined hardware architecture with low complexity for the SCL decoding, where the serial calculation and the pipelined operation are elegantly combined to strike a balance between the complexity and the latency. Moreover, we employ only one successive cancellation (SC) decoder core without L×L crossbars, and reduce the number of inputs of the metric sorter from 2L to L + 2. Finally, the FPGA implementations show that the hardware resource consumption is significantly reduced with negligible decoding performance loss.

A Parallel and Updatable Architecture for FPGA-Based Packet Classification With Large-Scale Rule Sets

As a programmable hardware, field-programmable gate array (FPGA) provides more opportunities for algorithmic network packet classification. Despite more than 10 years of research, the most actively investigated pipeline architectures still struggle to support fast rule search and efficient rule update for large-scale rule sets. In this article, we design and implement a novel architecture for multitree-based packet classification on FPGA, where the search and update processes are decoupled. A strategy of multi-processing elements (PEs), parallel search, and serial update is adopted. The parsing of multiple tree search results adopts a modular and hierarchical design, supporting architecture with various tree numbers. In addition, incremental rule updates can be achieved simply by traversing all PEs in one pass, with little and bounded impact on rule searching. Compared with TcbTree, the state-of-the-art updatable classifier, the experimental results on FPGA show that the classification performance of our design improves 3.4× on average for various 100k-scale rule sets.

Hardware acceleration of number theoretic transform for zk‐SNARK

AbstractZk‐SNARK unleashes the great potential of ZKP (zero‐knowledge proof) in the blockchain, distributed storage, and so forth. However, the proof‐generation of zk‐SNARK is excessively time intensive, making it a challenge to deploy a high‐performance zk‐SNARK in most real applications. As a result, NTT (Number Theoretic Transform), one of the most time‐consuming parts in proof‐generation, needs to be accelerated significantly. To address this issue, we propose a novel and efficient “data reordering" technique to enable a highly pipelined architecture, on which an FPGA‐based hardware accelerator is designed to support the large‐bitwidth and large‐scale NTT tasks in zk‐SNARK. This two‐level pipelined architecture can effectively reduce the data dependency and memory access requirements, meanwhile, can be flexibly scaled to different scales of FPGAs. To balance computing efficiency and flexibility, the OpenCL equipped with HLS is used to implement the heterogeneous acceleration system. We prototype the accelerator on the AMD‐Xilinx Alveo U50 card (UltraScale+ XCU50 FPGA). The evaluation results show that (1) our accelerator shows high scalability for different scales of FPGAs with a stable performance improvement; (2) it performs 1.95 faster than the one in PipeZK; (3) and it achieves 27.98 , 1.74 speedup and 6.9 , 6 energy efficiency improvement than AMD Ryzen 9 5900X single core and 12 cores respectively when integrated into the well‐known ZKP open‐source project, Bellman.

A Novel Strategy to Achieve Video Transcoding Using Cloud Computing

One of the fundamental challenges faced in deploying multimedia systems is delivering smooth and uninterrupted audio-visual information anywhere and anytime. In such systems, multimedia content is compressed within a certain format, this requires format conversion for various devices. Thus, a transcoding mechanism is required to make the content adaptive for various devices in the network. Video transcoding converts one digitally encoded format into another, this involves translating any file format containing video and audio at the same time. This is an essential feature for devices that do not support a specific format of media or have limited storage that requires a reduced file size. Through this paper, we provide a novel way of transcoding the block-based video coding schemes using cloud architecture by establishing a video pipelining architecture. The solution discussed in this paper would enable the end users to extract videos in any format and resolution seamlessly, combined with the scalability, reliability, and cost-effectiveness of the cloud. The proposed idea would be lucrative for all the video streaming applications that are currently relying on their legacy infrastructure for video transcoding.

A Benchmark for Dutch End-to-End Cross-Document Event Coreference Resolution

In this paper, we present a benchmark result for end-to-end cross-document event coreference resolution in Dutch. First, the state of the art of this task in other languages is introduced, as well as currently existing resources and commonly used evaluation metrics. We then build on recently published work to fully explore end-to-end event coreference resolution for the first time in the Dutch language domain. For this purpose, two well-performing transformer-based algorithms for the respective detection and coreference resolution of Dutch textual events are combined in a pipeline architecture and compared to baseline scores relying on feature-based methods. The results are promising and comparable to similar studies in higher-resourced languages; however, they also reveal that in this specific NLP domain, much work remains to be done. In order to gain more insights, an in-depth analysis of the two pipeline components is carried out to highlight and overcome possible shortcoming of the current approach and provide suggestions for future work.

VLSI Design Based on Block Truncation Coding for Real-Time Color Image Compression for IoT.

It has always been a major issue for a hospital to acquire real-time information about a patient in emergency situations. Because of this, this research presents a novel high-compression-ratio and real-time-process image compression very-large-scale integration (VLSI) design for image sensors in the Internet of Things (IoT). The design consists of a YEF transform, color sampling, block truncation coding (BTC), threshold optimization, sub-sampling, prediction, quantization, and Golomb-Rice coding. By using machine learning, different BTC parameters are trained to achieve the optimal solution given the parameters. Two optimal reconstruction values and bitmaps for each 4 × 4 block are achieved. An image is divided into 4 × 4 blocks by BTC for numerical conversion and removing inter-pixel redundancy. The sub-sampling, prediction, and quantization steps are performed to reduce redundant information. Finally, the value with a high probability will be coded using Golomb-Rice coding. The proposed algorithm has a higher compression ratio than traditional BTC-based image compression algorithms. Moreover, this research also proposes a real-time image compression chip design based on low-complexity and pipelined architecture by using TSMC 0.18 μm CMOS technology. The operating frequency of the chip can achieve 100 MHz. The core area and the number of logic gates are 598,880 μm2 and 56.3 K, respectively. In addition, this design achieves 50 frames per second, which is suitable for real-time CMOS image sensor compression.

Low-area and high-speed hardware architectures of KLEIN lightweight block cipher for image encryption

Internet of Things (IoT) connects a wide range of small devices over a large network, allowing for a wide range of applications. With the advancement of open-source public networks (such as IoT), image transmission for resource-constrained devices is becoming more insecure. In this paper, two hardware implementations for KLEIN block cipher are proposed that can provide security to encrypt different sets of images under resource-constrained applications (such as wireless sensor network, radio frequency identification, IoT etc.). An improvement in maximum operating frequency of 32.72% and 75.66% in the proposed serial and pipelined architectures is observed compared with the state-of-the-art design, respectively. The implemented pipelined architecture yields high throughput of 1840.15 MHz, and the serialized architecture implies 108 numbers of slices implemented on field-programmable gate array (FPGA) xc5vlx50t-3ff1136 device. On application-specific integrated circuit (ASIC) platform, the proposed serialized KLEIN implementation consumed less area in terms of gate equivalent. The existing solution was also subjected to changing correlation coefficients, number of pixels changing rate, unified average changing intensity, and entropy values. The simulation results validate the effectiveness of the performance of the proposed encryption scheme.

High-throughput and area-efficient architectures for image encryption using PRINCE cipher

Internet of Things (IoT) has gained popularity in recent years and has engulfed nearly every industry. The widespread use of numerous ubiquitous computing devices in the low-resource domain has resulted in a new set of privacy and security concerns. To address the problem of security in resource-constrained devices, many lightweight algorithms have been developed. This paper proposes optimized hardware implementations of the lightweight PRINCE block cipher, with the aim of providing adequate security while maximizing resource efficiency. The proposed architecture uses fewer resources and provides a reasonable trade-off between area footprint and efficiency. In the proposed unrolled pipelined architecture, the encryption round is divided into three sub-stages, with registers inserted in between. Using this design approach, the operating frequency is greatly improved. As a result, this architecture adapts itself effectively to high-performance applications. This paper also proposes serial-based and round-based architectures for resource-constrained devices. The proposed unrolled sub pipeline PRINCE block cipher is implemented on the Virtex-6-FF784 and Virtex-4-FF668 FPGA device families and achieved substantial improvements in throughput of 13.057% and 113%, respectively, as well as efficiency of 8.109% and 113.734% respectively. The proposed architecture is evaluated on a variety of grayscale images, and the security analysis is performed using MATLAB software. Aside from that, the proposed architecture uses the CBC-mode of operation. The security analysis and encryption outputs show that the proposed architecture is an effective choice for image encryption and provides sufficient security to the cipher images.

Fully fixed-point integrated digital circuit design of discrete memristive systems

In this paper, the fully fixed-point digital integrated circuits of discrete memristive systems are designed with very low circuit area cost, where the two-stage pipeline and multi-cycle architecture is employed. Firstly, the mathematical models of the discrete memristor and a memristor chaotic map are presented and dynamics are analyzed. Secondly, data flow design is carried out and the feasibility of the fixed-point model is discussed, which provides a foundation for the further circuit design. Thirdly, different architectures are designed and we get the optimal results. As a result, gate area of the discrete memristor is 40288 μm2 and the equivalent gate counts are 4588, while gate area of the discrete memristor map is 40424 μm2 and the equivalent gate counts are 4604. Moreover, a chaotic pseudo random sequence generator is designed and the NIST test is passed. It provides the foundation for the further applications of the discrete memristor and discrete memristor chaotic systems.

Real-Time Aerial Detection and Reasoning on Embedded-UAVs in Rural Environments

We present a unified pipeline architecture for a real-time detection system on an embedded system for UAVs. Neural architectures have been the industry standard for computer vision. However, most existing works focus solely on concatenating deeper layers to achieve higher accuracy with run-time performance as the trade-off. This pipeline of networks can exploit the domain-specific knowledge on aerial pedestrian detection and activity recognition for the emerging UAV applications of autonomous surveying and activity reporting. In particular, our pipeline architectures operate in a time-sensitive manner, have high accuracy in detecting pedestrians from various aerial orientations, use a novel attention map for multi-activities recognition, and jointly refine its detection with temporal information. Numerically, we demonstrate our model’s accuracy and fast inference speed on embedded systems. We empirically deployed our prototype hardware with full live feeds in a real-world open-field.

Reclassification of Mood Disorders with Comorbid Medical Diseases based on Sinai-Ruelle-Bowen/ SRB Entropy Measures

Background: Current classification systems ignore the family histories of patients and psychiatric and medical comorbidity. Methods: We study a new approach of applying spectral clustering to determine distinct bipolar disorder subtypes, which is data whose clusters are of various sizes and densities. We discovered clusters by processing a SRB (Sinai-Ruelle-Bowen) similarity matrix that reflects the proximity of Von Bertalanffy’s functions fitted to phase growth dynamics of EEG (electroencephalography) within a new pipeline architecture. For this purpose, 109 patients diagnosed with bipolar disorder according to DSM-V (Diagnostic and Statistical Manual of Mental Disorders, fifth edition) were evaluated in remission period cross-sectionally. Results: We found three distinct bipolar disorder subtypes with the p-values < 0.001. We exhibit mixing sub-shifts of EEG phase gradients such that there are chaotic phase transitions but higher order phase gradients in a cone basin is always strictly convex. More surprisingly, we show that the SRB entropy measures on some time interval although there exist several equilibrium states each corresponds to equilibrium state. Conclusion: It seems subtypes of the bipolar spectrum were shaped according to seasonality, comorbidity for anxiety disorder and presence of psychotic symptom.

An Integrated Real-Time FMCW Radar Baseband Processor in 40-nm CMOS

In this paper, a pipelined frequency-modulated continuous-wave (FMCW) radar baseband processor applied to real-time applications is proposed and implemented in 40-nm CMOS technology. The FMCW radar signal processing time is analyzed according to the system specifications. On the basis of the theoretical analysis and systematic considerations, a pipelined baseband architecture with internal single-port static random access memory (SRAM) is employed. The baseband processor is mainly composed of two-dimensional fast Fourier transform (2D-FFT), two-dimensional constant false alarm rate (2D-CFAR), digital beam-forming (DBF), and memory control modules. The 2D-FFT module is structured with a pipelined scheme and avoids the waste of data transferring time between modules. The 2D-CFAR module is programmable for different applications. The designed address control is proposed to depose the edge cells. The processor occupies a core chip area of 3.353 mm ×3.353 mm and has been tested on the personal computer (PC) and field programmable gate array (FPGA) platform. The power consumption and processing time are also analyzed and compared with other works. The processor consumes 55.65 mW, including SRAMs. The processing time is 12.67 ms with the maximum window size and 256 targets when operating at 125 MHz. This time is estimated based on the assumption that each chirp lasts for 0.04096 ms, and data input takes 10.48 ms. Within this period, the range FFT is completed. The Doppler FFT, 2D-CFAR with the maximum window size, and DBF with 256 targets require 0.80 ms, 1.16 ms, and 0.23 ms respectively.