Low-area and high-speed hardware architectures of KLEIN lightweight block cipher for image encryption

Abstract

Internet of Things (IoT) connects a wide range of small devices over a large network, allowing for a wide range of applications. With the advancement of open-source public networks (such as IoT), image transmission for resource-constrained devices is becoming more insecure. In this paper, two hardware implementations for KLEIN block cipher are proposed that can provide security to encrypt different sets of images under resource-constrained applications (such as wireless sensor network, radio frequency identification, IoT etc.). An improvement in maximum operating frequency of 32.72% and 75.66% in the proposed serial and pipelined architectures is observed compared with the state-of-the-art design, respectively. The implemented pipelined architecture yields high throughput of 1840.15 MHz, and the serialized architecture implies 108 numbers of slices implemented on field-programmable gate array (FPGA) xc5vlx50t-3ff1136 device. On application-specific integrated circuit (ASIC) platform, the proposed serialized KLEIN implementation consumed less area in terms of gate equivalent. The existing solution was also subjected to changing correlation coefficients, number of pixels changing rate, unified average changing intensity, and entropy values. The simulation results validate the effectiveness of the performance of the proposed encryption scheme.