Multistage pipelined architectures of Piccolo cipher for high-speed IoT applications

Abstract

Lightweight cryptography has become an obsession in recent times because of the rising security concerns in the field of smart connected devices having low resource prerequisites for Internet of Things (IoT) applications. The number of connected devices in IoT applications has been increasing throughout leaving severe security concerns. Result comparisons have been made with different block ciphers using 6-input and 4-input LUTs of the proposed work, which has been implemented for high-speed IoT and radio-frequency identification (RFID) applications. On the field programmable gate array (FPGA) platform, this work features topologies that give a 257% increase in throughput per area and a 21.9% increase in area. To improve the efficiency of the architectures, a multistage pipelined technique is used. Piccolo-80 and Piccolo-128 proposed architectures have provided throughput speeds of 1288.4 Mbps and 1046.1 Mbps on FPGA platforms, respectively. The proposed architecture is also implemented in application-specific integrated circuit (ASIC) 0.18 μm UMC technology, and the frequencies of Piccolo-80 and Piccolo-128 are 714.28 MHz and 649 MHz, respectively.