Pipeline Stages Research Articles

Artificial intelligence for dementia drug discovery and trials optimization.

Drug discovery and clinical trial design for dementia have historically been challenging. In part these challenges have arisen from patient heterogeneity, length of disease course, and the tractability of a target for the brain. Applying big data analytics and machine learning tools for drug discovery and utilizing them to inform successful clinical trial design has the potential to accelerate progress. Opportunities arise at multiple stages in the therapy pipeline and the growing availability of large medical data sets opens possibilities for big data analyses to answer key questions in clinical and therapeutic challenges. However, before this goal is reached, several challenges need to be overcome and only a multi-disciplinary approach can promote data-driven decision-making to its full potential. Herein we review the current state of machine learning applications to clinical trial design and drug discovery, while presenting opportunities and recommendations that can break down the barriers to implementation.

A Bandwidth-Efficient High-Performance RTL-Microarchitecture of 2D-Convolution for Deep Neural Networks

The computation complexity and huge memory access bandwidth of the convolutional layers in convolutional neural networks (CNNs) require specialized hardware architectures to accelerate CNN’s computations while keeping hardware costs reasonable for area-constrained embedded applications. This paper presents an RTL (Register Transfer Logic) level microarchitecture of hardware- and bandwidth-efficient high-performance 2D convolution unit for CNN in deep learning. The 2D convolution unit is made up of three main components including a dedicated Loader, a Circle Buffer, and a MAC (Multiplier-Accumulator) unit. The 2D convolution unit has a 2-stage pipeline structure that reduces latency, increases processing throughput, and reduces power consumption. The architecture proposed in the paper eliminates the reloading of both the weights as well as the input image data. The 2D convolution unit is configurable to support 2D convolution operations with different sizes of input image matrix and kernel filter. The architecture can reduce memory access time and power as well as execution time thanks to the efficient reuse of the preloaded input data, while simplifying hardware implementation. The 2D convolution unit has been simulated and implemented on Xilinx's FPGA platform to evaluate its superiority. Experimental results show that our design is 1.54× and 13.6× faster in performance than the design in [7] and [8], respectively, at lower hardware cost without using any FPGA’s dedicated hardware blocks. By reusing preloaded data, our design achieves a bandwidth reduction ratio between 66.4% and 90.5%.

PipePar: Enabling fast DNN pipeline parallel training in heterogeneous GPU clusters

Recently, pipeline parallelism for large-scale Deep Neural Network (DNN) training has been developed, which partitions the DNN model across multiple devices (e.g., GPUs) and improves the training efficiency by processing data divided into minibatches as a pipeline. However, existing model partitioning algorithms are mostly designed for homogeneous clusters with the same GPU devices and network connections (e.g., bandwidths), while heterogeneous GPU clusters are widely used in mainstream computing infrastructures. In heterogeneous environment, devices are equipped with different GPUs and network connections, and the efficiency of previous approaches is unsatisfactory due to the unbalanced load of the pipeline stages. In this paper, we propose PipePar, a model partitioning and task placement algorithm for pipeline parallel DNN training in heterogeneous GPU clusters. PipePar is based on dynamic programming with search space pruning that takes into consideration both the heterogeneity of GPUs and network bandwidth. PipePar can profile the DNN model for each type of GPU and conduct model partitioning and task placement based on given GPUs and network connections, which can optimize pipeline load balancing in heterogeneous environments and thus improve training efficiency. We design and implement a pipeline-based distributed deep learning training system in a heterogeneous GPU cluster and show through extensive experiments that PipePar outperforms the baseline approaches in the speed of large-scale DNN training.

Wire Length-Matching Aware Placement Method for Rapid Single Flux Quantum Logic Circuits

This paper proposes a fast automatic gate placement method for gate-level-pipelined Rapid Single Flux Quantum (RSFQ) circuits that are designed to have a high throughput. In such circuits, the gates in a pipeline stage are placed in a column and wires are routed in the area between adjacent columns. In wire routing, wire length-matching is performed. The proposed method performs gate placement for a given netlist to minimize the sum of the maximum distance between connected gates in each pair of adjacent columns. It leads to short wire extensions in wire length matching for increasing the operation frequency and small circuit area. The proposed method consists of a recursive procedure including two placements, selecting a pivot column, and determining the gate placement in the pivot column. The netlist is divided into two netlists with the pivot column. The recursive procedure performs gate placements for the two divided netlist. It is repeated until the location of every gate is determined. We implemented a placement tool by the proposed method and performed the gate placement for three circuits including several hundreds of gates. The proposed placement was 14 to 40 times faster than a placement based on simulated annealing where the sum of the maximum distance between connected gates is approximately the same.

Lowering Latency in a High-Speed Gate-Level-Pipelined Single Flux Quantum Datapath Using an Interleaved Register File

In this paper, we successfully demonstrate the 50-GHz operation of a microprocessor datapath based on single-flux-quantum (SFQ) logic with a gate-level pipeline (GLP) structure. The microprocessor datapath features a register file (RF), an arithmetic logic unit (ALU), and a long feedback loop that connects these components. Interleaved data-processing is applied in the RF. As the operating frequency of the RF is half that of the ALU, the timing constraints are eased; thus, we can reduce the number of pipeline stages used for timing adjustments. We designed a 4-bit datapath using the proposed technique, targeting 50-GHz operation. Compared to the conventional datapath, the total number of pipeline stages and the latency decreased from 49 to 24 and from 980 to 760 ps respectively. We fabricated test chips using the AIST Nb 9-layer 10-kA/cm <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$^{2}$</tex-math></inline-formula> process, and performed successful on-chip high-speed tests. In addition, our preliminary experiments suggest that we can expect 1.6-fold higher throughput at an 80-GHz clock frequency, at the cost of a 10% increase in latency.

Design and implementation of low power Advanced Encryption Standard cryptocore utilizing dynamic pipelined asynchronous model

The Advanced Encryption Standard (AES) has added new dimension to cryptography with its potentials of safeguarding the health care devices and systems. This paper presents the design of low power VLSI architecture for AES crypto application focusing on ECG signal transmission. The proposed design addresses the next generation cyber physical security requirement and low power for portable biomedical digital assistant devices. The proposed work utilizes on-chip built-in BRAM, configurable pipelining stages for combinational path, clock gating mechanism, and dynamic pipelined asynchronous operation. The use of dynamic pipelined asynchronous model (DPAM) controls different functional units of AES in controlled sequential order with gating of global clock and reset signals. This prevents unwanted switching activity in the functional units that waits for valid data. The performance of the proposed low power DPAM-AES architecture is compared with existing low power architectures in terms of power consumption, area, delay and throughput. The proposed DPAM-AES architecture results in power consumption starting from 260 mW to 329 mW, which are 47 mW to 385 mW lesser power for the frequencies of 100 MHZ to 800 MHZ respectively. The low power AES micro architecture is designed using VHDL and simulated, synthesized and implemented using Vivado design suite targeting ZynqSoC 7z020clg484-1 FPGA platform. The performance of the proposed AES micro architecture can be further improved by targeting to ASIC implementation of the designed AES core.

Automatic highlight detection in videos of martial arts tricking

We propose a novel strategy for the automatic detection of highlight events in user-generated tricking videos, to the best of our knowledge, the first one specifically tailored for this complex sport. Most current methods for related sports leverage high-level semantics such as predefined camera angles or common editing practices, or rely on depth cameras to achieve automatic detection. However, our approach only relies on the contents (themselves) in the frames of a given video, and consists in a four stage pipeline. The first stage identifies foreground key points of interest along with an estimation of their motion in the video frames. In the second stage, these points are grouped into regions of interest based on their proximity and motion. Their behavior over time is evaluated in the third stage to generate an attention map indicating the regions participating in the most relevant events. The fourth and final stage provides the extracted video sequences where highlights have been identified. Experimental results attest to the effectiveness of our approach, which shows high recall and precision values at frame level, with detections that fit well the ground truth events.

Robust ab initio solution of the cryo-EM reconstruction problem at low resolution with small data sets

Single particle cryo-electron microscopy has become a critical tool in structural biology over the last decade, able to achieve atomic scale resolution in three dimensional models from hundreds of thousands of (noisy) two-dimensional projection views of particles frozen at unknown orientations. This is accomplished by using a suite of software tools to (i) identify particles in large micrographs, (ii) obtain low-resolution reconstructions, (iii) refine those low-resolution structures, and (iv) finally match the obtained electron scattering density to the constituent atoms that make up the macromolecule or macromolecular complex of interest.Here, we focus on the second stage of the reconstruction pipeline: obtaining a low resolution model from picked particle images. Our goal is to create an algorithm that is capable of ab initio reconstruction from small data sets (on the order of a few thousand selected particles). More precisely, we propose an algorithm that is robust, automatic, and fast enough that it can potentially be used to assist in the assessment of particle quality as the data is being generated during the microscopy experiment.

VLSI Design of Saturation-Based Image Dehazing Algorithm

Hazy weather degrades the vividness of the images captured by real-time systems for applications such as object detection, remote sensing, and surveillance systems. This affects the performance of such real-time systems. The hardware implementation of a real-time haze removal system is imperative to solve these problems. Such a solution is proposed in this article. Here, the saturation-based hardware implementation of an image dehazing system is presented. To estimate atmospheric light more precisely, a <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$15\ttimes 15$</tex-math> </inline-formula> window minimum filter is implemented, which uses the downsampled hazy image to estimate the atmospheric light. Furthermore, we have employed saturation-based transmission map estimation, which makes our approach pixel-based rather than patch-based. Unlike existing patch-based methods, the proposed method requires neither an edge detection unit nor an image filtering unit to suppress halo artifacts around edges. The VLSI architecture of the proposed dehazing system comprises seven pipelined stages. It is implemented on FPGA as well as ASIC (65-nm technology node) platforms. The ASIC implementation of the proposed dehazing system yielded a maximum throughput of 624 Mpixels/s, which is fast enough to process <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$3840\ttimes 2160$</tex-math> </inline-formula> resolution at a rate higher than 70 fps with only 13.2k logic gates count.

JWST MIRI Flight Performance: Detector Effects and Data Reduction Algorithms

The detectors in the Mid-Infrared Instrument (MIRI) of the James Webb Space Telescope (JWST) are arsenic-doped silicon impurity band conduction (Si:As IBC) devices and are direct descendants of the Spitzer IRAC long wavelength arrays (channels 3 and 4). With appropriate data processing, they can provide excellent performance. In this paper we discuss the various non-ideal behaviors of these detectors that need to be addressed to realize their potential. We have developed a set of algorithms toward this goal, building on experience with previous similar detector arrays. The MIRI-specific stage 1 pipeline algorithms, of a three stage JWST calibration pipeline, were developed using pre-flight tests on the flight detectors and flight spares and have been refined using flight data. This paper describes these algorithms, which are included in the first stage of the JWST Calibration Pipeline for the MIRI instrument.

Neural Network-Based Recent Research Developments in SLAM for Autonomous Ground Vehicles: A Review

The development of autonomous vehicles has prompted an interest in exploring various techniques in navigation. One such technique is simultaneous localization and mapping (SLAM), which enables a vehicle to comprehend its surroundings, build a map of the environment in real-time, and locate itself within that map. Although traditional techniques have been used to perform SLAM for a long time, recent advancements have seen the incorporation of neural network techniques into various stages of the SLAM pipeline. This review paper provides a focused analysis of the recent developments in neural network techniques for SLAM-based localization of autonomous ground vehicles. In contrast to the previous review studies that covered general navigation and SLAM techniques, this work specifically addresses the unique challenges and opportunities presented by the integration of neural networks in this context. Existing review studies have highlighted the limitations of conventional visual SLAM, and this paper aims to explore the potential of deep learning methods. The paper discusses the functions required for localization, as well as several neural network-based techniques proposed by researchers to carry out such functions, are discussed. Firstly, it presents a general background of the issue, the relevant review studies that have already been done, and the adopted methodology in this review. Then, it provides a thorough review of the findings regarding localization and odometry. Finally, it presents our analysis of the findings, open research questions in the field, and a conclusion. A semi-systematic approach is used to carry out the review.

Provable Detection of Propagating Sampling Bias in Prediction Models

With an increased focus on incorporating fairness in machine learning models, it becomes imperative not only to assess and mitigate bias at each stage of the machine learning pipeline but also to understand the downstream impacts of bias across stages. Here we consider a general, but realistic, scenario in which a predictive model is learned from (potentially biased) training data, and model predictions are assessed post-hoc for fairness by some auditing method. We provide a theoretical analysis of how a specific form of data bias, differential sampling bias, propagates from the data stage to the prediction stage. Unlike prior work, we evaluate the downstream impacts of data biases quantitatively rather than qualitatively and prove theoretical guarantees for detection. Under reasonable assumptions, we quantify how the amount of bias in the model predictions varies as a function of the amount of differential sampling bias in the data, and at what point this bias becomes provably detectable by the auditor. Through experiments on two criminal justice datasets-- the well-known COMPAS dataset and historical data from NYPD's stop and frisk policy-- we demonstrate that the theoretical results hold in practice even when our assumptions are relaxed.

A Survey of Data Quality Requirements That Matter in ML Development Pipelines

The fitness of the systems in which Machine Learning (ML) is used depends greatly on good-quality data. Specifications on what makes a good-quality dataset have traditionally been defined by the needs of the data users—typically analysts and engineers. Our article critically examines the extent to which established data quality frameworks are applicable to contemporary use cases in ML. Using a review of recent literature at the intersection of ML, data management, and human-computer interaction, we find that the classical “fitness-for-use” view of data quality can benefit from a more stage-specific approach that is sensitive to where in the ML lifecycle the data are encountered. This helps practitioners to plan their data quality tasks in a manner that meets the needs of the stakeholders who will encounter the dataset, whether it be data subjects, software developers or organisations. We therefore propose a new treatment of traditional data quality criteria by structuring them according to two dimensions: (1) the stage of the ML lifecycle where the use case occurs vs. (2) the main categories of data quality that can be pursued (intrinsic, contextual, representational and accessibility). To illustrate how this works in practice, we contribute a temporal mapping of the various data quality requirements that are important at different stages of the ML data pipeline. We also share some implications for data practitioners and organisations that wish to enhance their data management routines in preparation for ML.

An Empirical Approach to Enhance Performance for Scalable CORDIC-Based Deep Neural Networks

Practical implementation of deep neural networks (DNNs) demands significant hardware resources, necessitating high computational power and memory bandwidth. While existing field-programmable gate array (FPGA)–based DNN accelerators are primarily optimized for fast single-task performance, cost, energy efficiency, and overall throughput are crucial considerations for their practical use in various applications. This article proposes a performance-centric pipeline Coordinate Rotation Digital Computer (CORDIC)–based MAC unit and implements a scalable CORDIC-based DNN architecture that is area- and power-efficient and has high throughput. The CORDIC-based neuron engine uses bit-rounding to maintain input-output precision and minimal hardware resource overhead. The results demonstrate the versatility of the proposed pipelined MAC, which operates at 460 MHz and allows for higher network throughput. A software-based implementation platform evaluates the proposed MAC operation’s accuracy for more extensive neural networks and complex datasets. The DNN accelerator with parameterized and modular layer-multiplexed architecture is designed. Empirical evaluation through Pareto analysis is used to improve the efficiency of DNN implementations by fixing the arithmetic precision and optimal pipeline stages. The proposed architecture utilizes layer-multiplexing, a technique that effectively reuses a single DNN layer to enhance efficiency while maintaining modularity and adaptability for integrating various network configurations. The proposed CORDIC MAC-based DNN architecture is scalable for any bit-precision network size, and the DNN accelerator is prototyped using the Xilinx Virtex-7 VC707 FPGA board, operating at 66 MHz. The proposed design does not use any Xilinx macros, making it easily adaptable for ASIC implementation. Compared with state-of-the-art designs, the proposed design reduces resource use by 45% and power consumption by 4× without sacrificing performance. The accelerator is validated using the MNIST dataset, achieving 95.06% accuracy, only 0.35% less than other cutting-edge implementations.

Evolving a Pipeline Approach for Abstract Meaning Representation Parsing Towards Dynamic Neural Networks.

Meaning Representation parsing aims to represent a sentence as a structured, Directed, Acyclic Graph (DAG), in an attempt to extract meaning from text. This paper extends an existing 2-stage pipeline AMR parser with state-of-the-art techniques in dependency parsing. First, Pointer-Generator Networks are used for out-of-vocabulary words in the concept identification stage, with an improved initialization via the use of word-and character-level embeddings. Second, the performance of the Relation Identification module is improved by jointly training the Heads Selection and the Arcs Labeling components. Last, we underline the difficulty of end-to-end training with recurrent modules in a static deep neural network construction approach and explore a dynamic construction implementation, which continuously adapts the computation graph, thus potentially enabling end-to-end training in the proposed pipeline solution.

Phenotyping of lymphoproliferative tumours generated in xenografts of non-small cell lung cancer.

Patient-derived xenograft (PDX) models involve the engraftment of tumour tissue in immunocompromised mice and represent an important pre-clinical oncology research method. A limitation of non-small cell lung cancer (NSCLC) PDX model derivation in NOD-scid IL2Rgammanull (NSG) mice is that a subset of initial engraftments are of lymphocytic, rather than tumour origin. The immunophenotype of lymphoproliferations arising in the lung TRACERx PDX pipeline were characterised. To present the histology data herein, we developed a Python-based tool for generating patient-level pathology overview figures from whole-slide image files; PATHOverview is available on GitHub (https://github.com/EpiCENTR-Lab/PATHOverview). Lymphoproliferations occurred in 17.8% of lung adenocarcinoma and 10% of lung squamous cell carcinoma transplantations, despite none of these patients having a prior or subsequent clinical history of lymphoproliferative disease. Lymphoproliferations were predominantly human CD20+ B cells and had the immunophenotype expected for post-transplantation diffuse large B cell lymphoma with plasma cell features. All lymphoproliferations expressed Epstein-Barr-encoded RNAs (EBER). Analysis of immunoglobulin light chain gene rearrangements in three tumours where multiple tumour regions had resulted in lymphoproliferations suggested that each had independent clonal origins. Overall, these data suggest that B cell clones with lymphoproliferative potential are present within primary NSCLC tumours, and that these are under continuous immune surveillance. Since these cells can be expanded following transplantation into NSG mice, our data highlight the value of quality control measures to identify lymphoproliferations within xenograft pipelines and support the incorporation of strategies to minimise lymphoproliferations during the early stages of xenograft establishment pipelines.

50-GFLOPS Floating-Point Adder and Multiplier Using Gate-Level-Pipelined Single-Flux-Quantum Logic With Frequency-Increased Clock Distribution

We demonstrate the functioning of a highthroughput, gate-level-pipelined floating-point adder and multiplier over 50 GHz. The gate-level-pipelined floating-point adder and multiplier requires dedicated circuit blocks to wait until other circuit blocks complete calculations because of the dependency between their sign, exponent, and significand parts. We revealed that the resultant delay difference of the waiting circuit blocks hinders high-frequency operation if the pre-designed circuit blocks with the fixed clock distribution are connected in a simple manner. We showed that clock distribution needs to synchronize with every pipeline stage regardless of the circuit blocks to minimize the delay difference between the circuit blocks for circuits containing the waiting circuit blocks (e.g., the floatingpoint adder and multiplier). We designed a 5-bit floating-point adder and multiplier to demonstrate the effectiveness of the clock distribution experimentally. The test chips were fabricated using AIST 10-kA/cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> Advanced Process 2. We verified the highspeed operation at over 50 GHz in the floating-point adder and multiplier. The maximum clock frequency and throughput of the floating-point adder were 56 GHz and 56 GFLOPS, respectively. The corresponding values for the floating-point multiplier were 63 GHz and 63 GFLOPS, respectively.

Unlocking the Potential of Quantum Machine Learning to Advance Drug Discovery

The drug discovery process is a rigorous and time-consuming endeavor, typically requiring several years of extensive research and development. Although classical machine learning (ML) has proven successful in this field, its computational demands in terms of speed and resources are significant. In recent years, researchers have sought to explore the potential benefits of quantum computing (QC) in the context of machine learning (ML), leading to the emergence of quantum machine learning (QML) as a distinct research field. The objective of the current study is twofold: first, to present a review of the proposed QML algorithms for application in the drug discovery pipeline, and second, to compare QML algorithms with their classical and hybrid counterparts in terms of their efficiency. A query-based search of various databases took place, and five different categories of algorithms were identified in which QML was implemented. The majority of QML applications in drug discovery are primarily focused on the initial stages of the drug discovery pipeline, particularly with regard to the identification of novel drug-like molecules. Comparison results revealed that QML algorithms are strong rivals to the classical ones, and a hybrid solution is the recommended approach at present.

Hyper-parameter tuning and feature extraction for asynchronous action detection from sub-thalamic nucleus local field potentials.

Decoding brain states from subcortical local field potentials (LFPs) indicative of activities such as voluntary movement, tremor, or sleep stages, holds significant potential in treating neurodegenerative disorders and offers new paradigms in brain-computer interface (BCI). Identified states can serve as control signals in coupled human-machine systems, e.g., to regulate deep brain stimulation (DBS) therapy or control prosthetic limbs. However, the behavior, performance, and efficiency of LFP decoders depend on an array of design and calibration settings encapsulated into a single set of hyper-parameters. Although methods exist to tune hyper-parameters automatically, decoders are typically found through exhaustive trial-and-error, manual search, and intuitive experience. This study introduces a Bayesian optimization (BO) approach to hyper-parameter tuning, applicable through feature extraction, channel selection, classification, and stage transition stages of the entire decoding pipeline. The optimization method is compared with five real-time feature extraction methods paired with four classifiers to decode voluntary movement asynchronously based on LFPs recorded with DBS electrodes implanted in the subthalamic nucleus of Parkinson's disease patients. Detection performance, measured as the geometric mean between classifier specificity and sensitivity, is automatically optimized. BO demonstrates improved decoding performance from initial parameter setting across all methods. The best decoders achieve a maximum performance of 0.74 ± 0.06 (mean ± SD across all participants) sensitivity-specificity geometric mean. In addition, parameter relevance is determined using the BO surrogate models. Hyper-parameters tend to be sub-optimally fixed across different users rather than individually adjusted or even specifically set for a decoding task. The relevance of each parameter to the optimization problem and comparisons between algorithms can also be difficult to track with the evolution of the decoding problem. We believe that the proposed decoding pipeline and BO approach is a promising solution to such challenges surrounding hyper-parameter tuning and that the study's findings can inform future design iterations of neural decoders for adaptive DBS and BCI.

Contactless Camera-Based Heart Rate and Respiratory Rate Monitoring Using AI on Hardware.

Detecting vital signs by using a contactless camera-based approach can provide several advantages over traditional clinical methods, such as lower financial costs, reduced visit times, increased comfort, and enhanced safety for healthcare professionals. Specifically, Eulerian Video Magnification (EVM) or Remote Photoplethysmography (rPPG) methods can be utilised to remotely estimate heart rate and respiratory rate biomarkers. In this paper two contactless camera-based health monitoring architectures are developed using EVM and rPPG, respectively; to this end, two different CNNs, (Mediapipe's BlazeFace and FaceMesh) are used to extract suitable regions of interest from incoming video frames. These two methods are implemented and deployed on four off-the-shelf edge devices as well as on a PC and evaluated in terms of latency (in each stage of the application's pipeline), throughput (FPS), power consumption (Watt), efficiency (throughput/Watt), and value (throughput/cost). This work provides important insights about the computational costs and bottlenecks of each method on each hardware platform, as well as which platform to use depending on the target metric. One of our insights shows that the Jetson Xavier NX platform is the best platform in terms of throughput and efficiency, while Raspberry Pi 4 8 GB is the best platform in terms of value.