Design and implementation of low power Advanced Encryption Standard cryptocore utilizing dynamic pipelined asynchronous model

Abstract

The Advanced Encryption Standard (AES) has added new dimension to cryptography with its potentials of safeguarding the health care devices and systems. This paper presents the design of low power VLSI architecture for AES crypto application focusing on ECG signal transmission. The proposed design addresses the next generation cyber physical security requirement and low power for portable biomedical digital assistant devices. The proposed work utilizes on-chip built-in BRAM, configurable pipelining stages for combinational path, clock gating mechanism, and dynamic pipelined asynchronous operation. The use of dynamic pipelined asynchronous model (DPAM) controls different functional units of AES in controlled sequential order with gating of global clock and reset signals. This prevents unwanted switching activity in the functional units that waits for valid data. The performance of the proposed low power DPAM-AES architecture is compared with existing low power architectures in terms of power consumption, area, delay and throughput. The proposed DPAM-AES architecture results in power consumption starting from 260 mW to 329 mW, which are 47 mW to 385 mW lesser power for the frequencies of 100 MHZ to 800 MHZ respectively. The low power AES micro architecture is designed using VHDL and simulated, synthesized and implemented using Vivado design suite targeting ZynqSoC 7z020clg484-1 FPGA platform. The performance of the proposed AES micro architecture can be further improved by targeting to ASIC implementation of the designed AES core.