Physics-based Compact Model Research Articles

High-Data-Rate Modulators Based on Graphene Transistors: Device Circuit Co-Design Proposals

The multifunctionality feature of graphene field-effect transistors (GFETs) is exploited here to design circuit building blocks of high-data-rate modulators by using a physics-based compact model. Educated device performance projections are obtained with the experimentally calibrated model and used to choose an appropriate improved feasible GFET for these applications. Phase-shift and frequency-shift keying (PSK and FSK) modulation schemes are obtained with 0.6 GHz GFET-based multifunctional circuits used alternatively in different operation modes: inverting and in-phase amplification and frequency multiplication. An adequate baseband signal applied to the transistors’ input also serves to enhance the device and circuit performance reproducibility since the impact of traps is diminished. Quadrature PSK is also achieved by combining two GFET-based multifunctional circuits. This device circuit co-design proposal intends to boost the heterogeneous implementation of graphene devices with incumbent technologies into a single chip: the baseband pulses can be generated with CMOS technology as a front end of line and the multifunctional GFET-based circuits as a back end of line.

Physics-based compact current model for schottky barrier transistors at deep cryogenic temperatures including band tail effects and quantum oscillations

This paper presents a compact model for the DC current of Schottky barrier field-effect transistors at deep cryogenic temperatures, close to absolute zero kelvin. The proposed model is physics based and calculates the injection current over a device’s Schottky barriers, by considering physical effects at these temperatures (e.g. quantum oscillations, band tail effect, phonon-assisted tunneling, etc.). For model verification, it is compared to measurements performed on nanowire Schottky barrier transistors at a temperature of 5.5K.

A Physics-Based Compact DC Model for AOS TFTs Considering Effects of Active Layer Thickness Variation

A Physics-Based Compact DC Model for AOS TFTs Considering Effects of Active Layer Thickness Variation

A Physics-Based Compact Model for the Static Drain Current in Heterojunction Barrier CNTFETs—Part II: Scattering, High-Field Effects, and Model Verification

A Physics-Based Compact Model for the Static Drain Current in Heterojunction Barrier CNTFETs—Part II: Scattering, High-Field Effects, and Model Verification

Maximizing output power in P-N junction betavoltaic batteries via Monte Carlo and Physics-Based Compact Model Co-Simulation*

Maximizing output power in P-N junction betavoltaic batteries via Monte Carlo and Physics-Based Compact Model Co-Simulation*

A Physics-Based Compact Model for the Static Drain Current in Heterojunction Barrier CNTFETs—Part I: Barrier-Related Current

A Physics-Based Compact Model for the Static Drain Current in Heterojunction Barrier CNTFETs—Part I: Barrier-Related Current

Characterization and Modeling of 14-/16-nm FinFET-Based LDMOS

Due to the significant advancement of system-on-chip (SoC) based architectures in IC technology, FinFET-based laterally diffused MOS (LDMOS) FETs are crucial for integrating high-voltage (HV) devices with low-voltage (LV) FinFET-based digital systems. We have performed on-wafer characterization of the state-of-the-art production level 14-/16-nm FinFET-based LDMOS devices. Industry-standard FinFET’s compact model Berkeley short-channel IGFET model-common multigate (BSIM-CMG) 111.1.0 cannot model the electrical characteristics of these devices accurately. We have developed a physics-based compact model for the overlap charge and voltage-dependent resistance of the drift region. The proposed model has been implemented in Verilog-A and added to the existing BSIM-CMG model. The improved BSIM-CMG model shows excellent agreement with the experimental data for the transcapacitances, current, and its derivatives. To the best of our knowledge, this is the first charge-based compact model presented for multigate LDMOS devices.

Physics-Based Compact Model of Independent Dual-Gate BEOL-Transistors for Reliable Capacitorless Memory

Physics-Based Compact Model of Independent Dual-Gate BEOL-Transistors for Reliable Capacitorless Memory

Ternary Łukasiewicz logic using memristive devices

Memristive devices based on the Valence Change Mechanism (VCM) are promising devices for storage class memory, neuromorphic computing and logic-in-memory (LIM) applications. They are suited for such a wide range of applications, due to their possibility for extreme dense integration, low power consumption and multilevel capabilities. Through LIM concepts, Boolean logic operations can be performed directly in memory. In many of these concepts, the resistance state of the device is interpreted as the logical input and output of the logic function, which is why these concepts are called ‘stateful’ logic. Most of the proposed ideas, however, are defined based on only binary switching VCM devices and neglect their multi-level capabilities. Extending LIM concepts towards multinary logic, e.g. a ternary logic, would increase the data density inside the memory array and reduce the number of devices required to perform a certain operation. In this work, we discuss two possibilities of realizing a ternary logic based on the analog switching in the RESET or in the SET direction. For both directions we verify the logic functionality by showing the basic operations of implication, negation and false operation, which together form a functionally complete logic. Additionally, for both switching directions, we discuss a 41-Trit ( 64-Bit) addition. For all investigations the physics-based compact model JART VCM v1b is used, which has been verified on the RESET direction multilevel properties of the TaO devices.

Modeling Analysis of BTI-Driven Degradation of a Ring Oscillator Designed in a 28-nm CMOS Technology

With tightening reliability margins, product-level aging analysis is gradually gaining impetus and is set to become an integral part of the modern design flow. Increased emphasis is placed on the development of physics-based compact models for the phenomena responsible for transistor degradation and their integration into EDA environments. Commercial Process Design Kits (PDKs) of advanced technologies have also started to include compact models for transistor degradation along with a dedicated reliability simulation framework. In this work, we present a comprehensive study of the compact aging models in one such commercial PDK, with the help of extensive measurement data from individual devices as well as Ring Oscillators (RO). Then, we perform our own extraction of model parameter shifts from full Id-Vgs fitting of the measured BTI-stressed devices to gain insight into the modeling procedure adopted by the foundry. We finally use the parameters extracted thusly to investigate the impact of the time-0 and the time-dependent device-to-device variability on RO degradation.

Compact I-V model for back-gated and double-gated TMD FETs

A physics-based analytical DC compact model for double and single gate TMD FETs is presented. The model is developed by calculating the charge density inside the 2D layer which is expressed in terms of the Lambert W function that recently has become the standard in SPICE simulators. The current is then calculated in terms of the charge densities at the drain and source ends of the channel. We validate our model against measurement data for different device structures. A superlinear current increase above certain gate voltage has been observed in some MoS2 FET devices, where we present a new mobility model to account for the observed phenomena. Despite the simplicity of the model, it shows very good agreement with the experimental data.

Compact modeling of Schottky barrier field-effect transistors at deep cryogenic temperatures

In this paper, a physics-based DC compact model for Schottky barrier field-effect transistors at deep cryogenic temperatures is presented. The model uses simplified tunneling equations at temperatures of ϑ≈0K in order to calculate the field emission injection current at the device’s Schottky barriers. Additionally, an empirical expression for including resonant tunneling effects is introduced. The compact model is also compared to and verified by measurements performed on ultra-thin body and buried oxide SOI Schottky barrier field-effect transistors and is able to capture the signature of resonant tunneling effects in the transfer characteristics.

A physics-based compact model of thermal resistance in RRAMs

In this paper, we present a physics-based compact model of thermal resistance in Resistive Random-Access Memory (RRAM) devices considering (a) thermal properties of electrode materials, (b) temperature-induced variations in material thermal conductivity, and (c) parasitic heat losses through the oxide surrounding the filament. Fully coupled numerical simulation data obtained from the self-consistent solution of the drift-diffusion equation (for vacancy migration), carrier continuity equation (for electronic conduction), and the Fourier heat diffusion equation (accounting for electro-thermal heating) has been used for developing and validating the proposed model. Excellent agreement is observed between the model and the numerical simulation results. The proposed model is validated with experimentally measured conductive filament temperature obtained from two different temperature sensing methods. Finally, we present a modeling framework to estimate the potential thermal-cross talk in RRAM crossbar arrays. Our results illustrate that a power-dependent thermal resistance model significantly improves the accuracy in estimating the electro-thermal effects in RRAMs.

A Quantum Corrected Compact Model of Experimentally Fabricated GAA 2-D MBCFETs

Gate all around (GAA) 2-D material multibridge-channel (MBC) FET with the thinnest channel could lead to the ultimate scaling of transistor technology. In this work, a physics-based compact model including quantum correction and multiple other physical effects is developed for experimentally fabricated 2-D MBC FET. The model is formulated on the basis of symmetric double gate (DG) potential solutions. By considering the wave functions in the 2-D channel, the quantum mechanical confinement (QMC) is taken into account, and the quantum corrected potential is deduced in analytical form using perturbation approach. The model captures the carrier density distribution across channel accurately, which has been verified by first principle calculations. Furthermore, electrical characteristics, such as <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${I}$ </tex-math></inline-formula> – <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}$ </tex-math></inline-formula> and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${C}$ </tex-math></inline-formula> – <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}$ </tex-math></inline-formula> models, are created. The models are implemented in Verilog-A and they show good agreement with experimental data.

A Physics-Based Compact Model to Capture Cryogenic Behavior of LDMOS Transistors

In this work, a detailed characterization of lateral DMOS transistors in the cryogenic regime is carried out. It is shown that carrier freeze-out in the drift region is responsible for increased ON-resistance for temperatures lower than a transition temperature, which is independent of device dimensions. The carrier freeze-out affects the operation of laterally diffused MOS (LDMOS) transistors in the linear region but not in the saturation region due to field-assisted ionization. A peak behavior in output conductance is also observed at cryogenic temperatures. The physics behind these observed anomalous behaviors is studied in detail and modeled. The industry-standard HiSIM_HV2 model is augmented with new equations to extend the model accuracy to 77 K. The accuracy of the model is verified with the data measured from LDMOS transistors with different dimensions. The model accurately captures the device behavior in the 77–300 K temperature range and demonstrates excellent scalability.

MOSFET Physics-Based Compact Model Mass-Produced: An Artificial Neural Network Approach

The continued scaling-down of nanoscale semiconductor devices has made it very challenging to obtain analytic surface potential solutions from complex equations in physics, which is the fundamental purpose of the MOSFET compact model. In this work, we proposed a general framework to automatically derive analytical solutions for surface potential in MOSFET, by leveraging the universal approximation power of deep neural networks. Our framework incorporated a physical-relation-neural-network (PRNN) to learn side-by-side from a general-purpose numerical simulator in handling complex equations of mathematical physics, and then instilled the "knowledge'' from the simulation data into the neural network, so as to generate an accurate closed-form mapping between device parameters and surface potential. Inherently, the surface potential was able to reflect the numerical solution of a two-dimensional (2D) Poisson equation, surpassing the limits of traditional 1D Poisson equation solutions, thus better illustrating the physical characteristics of scaling devices. We obtained promising results in inferring the analytic surface potential of MOSFET, and in applying the derived potential function to the building of 130 nm MOSFET compact models and circuit simulation. Such an efficient framework with accurate prediction of device performances demonstrates its potential in device optimization and circuit design.

A Physics-Based Dynamic Compact Model of Ferroelectric Tunnel Junctions

In this letter, we proposed a dynamic compact model for metal-ferroelectric-semiconductor (MFS) ferroelectric tunnel junctions (FTJ) based on their device physics. The voltage control over dynamic polarizations and the semiconductor surface potentials is achieved for full-region operations, supporting complex FTJ state transitions. A unified and smooth current model across different regions was proposed by formulating tunneling transports in FTJ with complicated barrier shapes from the first-principle tunneling theory. The model was extensively verified with both experimental data and technology computer-aided design (TCAD) simulations, featuring accurate descriptions of multi-states, frequency dependent programming, and circuit simulations.

A Study of the Electroforming Process in 1T1R Memory Arrays

For reproducible resistive switching in memristive devices, electroforming is a crucial process. However, a deeper understanding of the electroforming process is still lacking due to unavailability of a proper simulation tool. Here, we propose a physics-based compact model for the electroforming of valence change mechanism (VCM) memristive devices. The developed JART VCM Forming model is experimentally validated with the ZrOx-based memristive device. Furthermore, the electroforming process in different 1T1R memristive arrays is simulated with this model. The study shows that the electrical characteristics of each device in the array after the forming process are influenced by word/bit line series resistance. In addition, control effects depending on the channel width and applied gate voltage of transistor in the 1T1R cell are also investigated with the compact model simulation.

Comprehensive Physical Commutation Characteristic Analysis and Test of Hybrid Line Commutated Converter Based on Physics Compact Model of IGCT

In order to mitigate commutation failure of high voltage direct current (HVdc) system, a novel hybrid line commutated converter (H-LCC) based on integrated gate commutated thyristor (IGCT) and thyristor has been proposed. To verify the proposed scheme's effectiveness and correctness, the physics-based compact model of reverse blocking IGCT (RB-IGCT) and physics-based model of thyristor are established in this article. By comparing the features of physics-based model with other simulation methods, it can be observed that the former has obvious advantages. On the basis, a simulation study of proposed H-LCC based on physics compact model of RB-IGCT and physics-based model of thyristor is conducted to analyze the physical commutation characteristics comprehensively, which is verified by equivalent commutation tests. The H-LCC can mitigate commutation failure of HVdc effectively and physics-based model of H-LCC is expected to be applied in the simulation of dc grid equipment and provide reference for commutation characteristics analysis and snubber parameter optimization that need rapid and multiple simulations.

A Reliability-Enhanced Differential Sensing Amplifier for Hybrid CMOS/MTJ Logic Circuits

Recently, hybrid logic circuits based on magnetic tunnel junctions (MTJs) have been widely investigated to realize zero standby power. However, such hybrid CMOS/MTJ logic circuits suffer from a severe sensing reliability due to the limited tunnel magnetoresistance ratio (TMR ≤ 150%) of the MTJ and the large process variation in the deep sub-micrometer technology node. In this paper, a novel differential sensing amplifier (DSA) is proposed, in which two PMOS transistors are added to connect the discharging branches and evaluation branches. Owing to the positive feedback realized by these two added PMOS transistors, it can achieve a large sensing margin. By using an industrial CMOS 40 nm design kit and a physics-based MTJ compact model, hybrid CMOS/MTJ simulations have been performed to demonstrate its functionality and evaluate its performance. Simulation results show that it can achieve a smaller sensing error rate of 9% in comparison with the previously proposed DSAs with a TMR ratio of 100% and process variation of 10%, while maintaining almost the same sensing delay of 74.5 ps and sensing energy of 1.92 fJ/bit.