Abstract
Due to the significant advancement of system-on-chip (SoC) based architectures in IC technology, FinFET-based laterally diffused MOS (LDMOS) FETs are crucial for integrating high-voltage (HV) devices with low-voltage (LV) FinFET-based digital systems. We have performed on-wafer characterization of the state-of-the-art production level 14-/16-nm FinFET-based LDMOS devices. Industry-standard FinFET’s compact model Berkeley short-channel IGFET model-common multigate (BSIM-CMG) 111.1.0 cannot model the electrical characteristics of these devices accurately. We have developed a physics-based compact model for the overlap charge and voltage-dependent resistance of the drift region. The proposed model has been implemented in Verilog-A and added to the existing BSIM-CMG model. The improved BSIM-CMG model shows excellent agreement with the experimental data for the transcapacitances, current, and its derivatives. To the best of our knowledge, this is the first charge-based compact model presented for multigate LDMOS devices.
Sign-in/Register to access full text options 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
