Ternary Łukasiewicz logic using memristive devices

Abstract

Memristive devices based on the Valence Change Mechanism (VCM) are promising devices for storage class memory, neuromorphic computing and logic-in-memory (LIM) applications. They are suited for such a wide range of applications, due to their possibility for extreme dense integration, low power consumption and multilevel capabilities. Through LIM concepts, Boolean logic operations can be performed directly in memory. In many of these concepts, the resistance state of the device is interpreted as the logical input and output of the logic function, which is why these concepts are called ‘stateful’ logic. Most of the proposed ideas, however, are defined based on only binary switching VCM devices and neglect their multi-level capabilities. Extending LIM concepts towards multinary logic, e.g. a ternary logic, would increase the data density inside the memory array and reduce the number of devices required to perform a certain operation. In this work, we discuss two possibilities of realizing a ternary logic based on the analog switching in the RESET or in the SET direction. For both directions we verify the logic functionality by showing the basic operations of implication, negation and false operation, which together form a functionally complete logic. Additionally, for both switching directions, we discuss a 41-Trit ( 64-Bit) addition. For all investigations the physics-based compact model JART VCM v1b is used, which has been verified on the RESET direction multilevel properties of the TaO devices.