Physics-based Compact Model Research Articles

Compact Subthreshold Current Modeling of Short-Channel Nanoscale Double-Gate MOSFET

A physics-based compact subthreshold current model for short-channel nanoscale double-gate MOSFETs is presented. The potential is modeled using conformal mapping techniques in combination with parabolic approximations. For subthreshold conditions, we have assumed that the electrostatics is dominated by capacitive coupling between the body electrodes. Hence, the potential is obtained as an analytical solution of the 2-D Laplace equation. The current modeling is based on drift-diffusion theory. The modeling results are in good agreement with those of numerical simulations without the use of adjustable parameters.

Delay Correction for Accurate Extraction of Time Exponent and Activation Energy of NBTI

Negative-bias temperature instability (NBTI) represents one of the most severe reliability issues for pMOS transistors in logic and analog applications. Accurate reliability predictions require physically based models for NBTI and accurate methods for the estimation of time and temperature kinetic parameters, namely, the power-law time exponent and the activation energy. Describing on-the-fly degradation data by power-law time dependence and Arrhenius thermal activation, we present here a new methodology for estimating the power-law exponent and the activation energy. This allows for physics-based compact models and reliability extrapolations of NBTI.

A Compact Model for Undoped Silicon-Nanowire MOSFETs With Schottky-Barrier Source/Drain

A comprehensive physics-based compact model for three-terminal undoped Schottky-barrier (SB) gate-all-around silicon-nanowire MOSFETs is formulated based on a quasi-2-D surface-potential solution and the Miller-Good tunneling model. The energy-band model has accounted for the screening of the gate field by the electrons or holes, which has been largely missed in the literature. Although SB-MOSFETs are essentially ambipolar devices, we show that the separate modeling of electron and hole currents is simple yet accurately predicts the final ambipolar current. Thinner oxide thickness is confirmed to be beneficial to SB-MOSFETs for both ON - and OFF-state currents. However, smaller nanowire radius (or thinner body thickness) is found to be only beneficial to SB-MOSFETs with high SB heights (SBHs) despite the OFF-state current being reduced significantly. For SB-MOSFETs with low SBHs, the tunneling-current-density enhancement due to a smaller radius is not able to compensate the reduction in the contact size, which leads to a degradation of the ldquoONrdquo current. The drift current in the channel is shown to be negligible in SB-MOSFETs, and the tunneling/thermionic current through the SB represents the main current-limiting mechanism.

Novel simulation approach for transient analysis and reliable thermal management of power devices

This paper deals with a novel simulation approach, which enables to take into consideration at the same time local and global effects that are not easily simulated by the traditional techniques based on finite elements. The proposed method combines physics-based compact models of semiconductor devices with a distributed three-dimensional description of the thermal problem within a unified simulation environment. The performance of the new approach is demonstrated in the case of the simulation of thermal instabilities, which undermines the reliability of high power IGBTs.

Computationally Efficient Physics-Based Compact CNTFET Model for Circuit Design

We present a computationally efficient physics-based compact model designed for the conventional CNTFET featuring a MOSFET-like operation. A large part of its novelty lies on the implementation of a new analytical model of the channel charge. In addition, Boltzmann Monte Carlo (MC) simulation is performed with the challenge to cross-link this simulation technique to the compact modeling formulation. The comparison of the electrical characteristics obtained from the MC simulation and from the compact modeling demonstrates the compact model accuracy within its range of validity. Then, from a study of the CNT diameter dispersion for three technological processes, the compact model allows us to determine the CNTFET threshold voltage distribution and to evaluate the resulting dispersion of the propagation delay from the simulation of a ring oscillator.

An industrial view on compact modeling

Compact modeling is an area that gets more and more mature. Collaborations and standardization efforts have emerged. In this paper we present some special requirements that are important when constructing physics-based compact models. We will substantiate our statements on two recent examples, an inductor model and a MOSFET model.

Explicit compact model for symmetric double-gate MOSFETs including solutions for small-geometry effects

A physics-based compact model including short-channel effects (SCEs) is presented for undoped (or lightly doped) symmetric double-gate (DG) MOSFETs. Our approach allows an accurate description of the device behavior down to 60 nm with a simple set of equations. It is shown that the subthreshold current, the threshold voltage roll-off and the DIBL predicted by the analytical solution are in close agreement with 2-D numerical simulations performed with Atlas. The mobility degradation due to both transverse and longitudinal fields is taken into account but the channel length modulation (saturation regime) is not addressed in this paper. In order to demonstrate that the model is well-suited for circuit simulation, the results of the dynamic model based on an explicit formulation of the mobile charge density are also presented.

Physics-based wideband predictive compact model for inductors with high amounts of dummy metal fill

A computationally efficient physics-based wideband predictive inductor compact model is presented that is capable of evaluating the impact on inductance and quality factor of dummy metal fill-cells. In a modern integrated-circuit process, high amounts of these fill-cells are required to meet metal density rules and guarantee adjacent circuit integrity. The predictions made with this model are shown to be in agreement with data measured on symmetrical octagonal inductors realized in a 90-nm CMOS process with varying amounts of dummy metal fill-cells. We further provide all inductance equations, list additional sources of eddy current losses, and discuss layout modifications, which would further improve the performance of the integrated inductors

Reliability analysis and modeling of power MOSFETs in the 42-V-PowerNet

This paper analyzes the operation of PowerMOSFETs in the 42-V-PowerNet and shows that very stressful conditions are encountered, which can lead to severe reliability problems. To enable thorough investigations by circuit simulations an accurate physics-based compact model of the devices is proposed: it includes all important electrothermal effects relevant to the description of the observed failure mechanisms. By means of an advanced thermal-modeling approach, multichip assemblies can be accurately described, including mutual heating effects between neighboring devices. Some properly chosen examples demonstrate the validity of the model and its usefulness for reliability investigations

A computationally efficient physics-based compact bipolar transistor model for circuit Design-part II: parameter extraction and experimental results

A compact bipolar transistor model was presented in Part I that combines the simplicity of the SPICE Gummel-Poon model (SGPM) with some major features of HICUM. The new model, called HICUM/L0, is more physics-based and accurate than the SGPM but at the same time, from a computational point of view, suitable for simulating large circuits. In Part II, a parameter determination procedure is described and demonstrated for a variety of SiGe process technologies.

A computationally efficient physics-based compact bipolar transistor model for circuit Design-part I: model formulation

A compact bipolar transistor model is presented that combines the simplicity of the SPICE Gummel-Poon model (SGPM) with some major features of HICUM. The new model, called HICUM/L0, is more physics-based and accurate than the SGPM and at the same time, from a computational point of view, suitable for simulating large circuits. The new model has been implemented in Verilog-A and, as compiled code, in various commercial circuit simulators. In Part I, the fundamental model formulation is presented along with a derivation of the most important equations. Experimental results are shown in Part II.

Design and Modeling of High-Impedance Electromagnetic Surfaces for Switching Noise Suppression in Power Planes

This paper presents a detailed design and modeling approach for power planes with integrated high-impedance electromagnetic surfaces (HIS). These novel power planes, which were introduced recently, have the unique ability of providing effective broadband simultaneous switching noise (SSN) mitigation. Full-wave electromagnetic simulation is used to study the impact of the geometry on the performance of these novel power planes. It is demonstrated that power planes using inductance-enhanced HIS can be designed for broadband mitigation of the SSN from the upper hundred megahertz to the gigahertz frequencies. Physics-based compact models for the unit cell of power planes with integrated HIS are developed and several of them connected in a two-dimensional array to build full models for large and multilayer power planes. The compact model offers fast analysis of power planes. As an example, we show that the full-wave simulation time of a 10/spl times/10 cm power plane with integrated HIS can be dramatically reduced from 24 to 48 h using a commercially available three-dimensional full-wave solver to less than 1 min when using the compact circuit model developed here.

Physics-Based Compact Model of Nanoscale MOSFETs—Part I: Transition From Drift-Diffusion to Ballistic Transport

In this paper, we present a physics-based analytical model for nanoscale MOSFETs that allows us to seamlessly cover the whole range of regimes from drift-diffusion (DD) to ballistic (B) transport, taking into account quantum confinement in the channel. In Part I we focus on MOSFETs with ultrathin bodies, in which quantum confinement is structural rather than field-induced, and investigate in detail an analytical description of the transition from drift-diffusion to B transport based on the Bu/spl uml/ttiker approach to dissipative transport. We first start from the derivation of a closed form analytical expression of the Natori model for B MOSFETs, and show that a MOSFET with finite scattering length can be described as a suitable chain of B MOSFETs. Then, we are able to compact the behavior of the B chain in a simple analytical model. In the derivation, we also find a similarity between the B limit in the chain and the saturation velocity effect, that leads us to propose an alternative implementation of the saturation velocity effect in compact models.

Physics-Based Compact Model of Nanoscale MOSFETs—Part II: Effects of Degeneracy on Transport

In this paper, we extend our derivation of an analytical model for nanoscale MOSFETs, focusing on the effects of Fermi-Dirac statistics on vertical electrostatics and on carrier transport. We derive a relation between mobility and mean-free path valid under degenerate statistics, and investigate the cases of rectangular and triangular quantum confinement under Fermi-Dirac statistics in the transition from DD to B transport. We derive a simple, physics-based and continuous analytical model that describes double-gate MOSFETs, fully depleted silicon-on-insulator MOSFETs, and bulk MOSFETs in the electric quantum limit in the whole range of transport regimes comprised between DD (device length much larger than mean-free path) and B (device length much smaller than mean-free path).

Transient modelling of single-electron transistors for efficient circuit simulation by SPICE

In the paper, a regime, where the independent treatment of single-electron transistors (SETs) in transient simulations is valid, has been identified quantitatively. It is found that, as in the steady-state case, although the temperature varies, each SET can be treated independently, even in the transient case when the interconnection capacitance is large enough. However, the value of the load capacitance CL of the interconnections for the independent treatment of SETs is approximately ten times larger than that of the steady-state case. A compact SET transient model is developed for transient circuit simulation by SPICE. The developed model is based on a linearised equivalent circuit and the solution of a master equation is done by the programming capabilities of the SmartSpice. Exact delineation of several simulation time scales and the physics-based compact model make it possible to accurately simulate hybrid circuits in the timescales down to several tens of picoseconds.

SP: an advanced surface-potential-based compact MOSFET model

This work describes an advanced physics-based compact MOSFET model (SP). Both the quasistatic and nonquasi-static versions of SP are surface-potential-based. The model is symmetric, includes the accumulation region, small-geometry effects, and has a consistent current and charge formulation. The surface potential is computed analytically and there are no iterative loops anywhere in the model. Availability of the surface potential in the source-drain overlap regions enables a physics-based formulation of the extrinsic model (e.g., gate tunneling current) and allows for a noise model free of discontinuities or unphysical interpolation schemes. Simulation results are used to illustrate the interplay between the model structure and circuit design.

A Surface Potential-Based Compact Model of n-MOSFET Gate-Tunneling Current

Aggressive scaling of the gate-oxide thickness has made gate-tunneling current an essential aspect of MOSFET modeling. This work presents a novel physics-based compact model of gate current in the n-MOSFET. A simplified version of the Esaki-Tsu formula is developed to calculate the tunneling current density, in which the original integral is approximated to retain the essential physics without sacrificing computational efficiency required in a compact model. The proposed model is surface potential-based in both the channel and source/drain overlap regions. The channel component of the gate current is physically partitioned into the source and drain parts using a symmetrically linearized version of the charge-sheet model. The partition is implemented in analytical form and accounts for the drain bias dependence of the channel component. A small number of adjustable parameters is sufficient to reproduce the experimentally observed bias and geometry dependence of the gate current for several advanced processes.

Performance assessment of scaled strained-Si channel-on-insulator (SSOI) CMOS

The device/circuit performance of strained-Si (SS) MOSFETs including strained-Si channel-on-insulator (SSOI) is assessed via a physics-based compact model calibrated against fabricated 70 nm strained and unstrained (control) Si devices. With emphasis on SS device specific features, mobility enhancement and band offsets, and SOI advantages, dynamic floating-body effects and no areal junction capacitance, the speed superiority of SSOI CMOS is discussed. Device design point and performance trade-off are presented as well, thus allowing exploitation of maximum performance in the SS devices.

The missing link to seamless simulation

This paper reviews the trends and needs in multilevel modeling in the context of nanometer CMOS ULSI systems, with an emphasis from the model/tool developer's perspective. A dual representation of the transistors/circuit is proposed and demonstrated through physics-based compact modeling and a single-engine circuit simulator based on subcircuit expansion. Extension to process correlation and block-level representation is also proposed, which will be the key to studying process effects on system performance. This consistent dual representation allows detailed physics captured at a lower level to be propagated to the higher level of abstraction. The key idea is to build a physics-based device compact model (CM) based on technology characterization, which serves as the building block for an implicit multilevel circuit simulator based on a subcircuit-expansion approach. In this way, process variation can be captured through device CMs, and its effects on circuit/system performance can be linked to a consistent hierarchy of abstractions within the same simulator engine.

Double jeopardy in the nanoscale court [MOSFET modeling

Physics-based compact short-channel models of threshold voltage and subthreshold swing for undoped symmetric double-gate MOSFETs are presented, developed from analytical solutions of the two-dimensional Poisson equations in the channel region. These models accurately characterize the subthreshold and near-threshold regions of operation by appropriately including essential phenomena such as volume inversion and the dominance of mobile charges over fixed charges under threshold conditions. Explicit, analytical expressions are derived for a scale length, which results from an evanescent-mode analysis. These equations readily quantify the impact of silicon film thickness and gate oxide thickness on the minimum channel length and device characteristics and can be used as an efficient guideline for device designs. These newly developed models are exploited to make a comprehensive projection on the scaling limits of undoped double-gate MOSFETs. On the individual device level, model predictions indicate that the minimum channel length can be scaled beyond 10 nm for a turn-off behavior of S=100 mV/dec for a silicon film thickness below 5 nm and an electrical equivalent oxide thickness below 1 nm.