Physical Unclonable Functions Responses Research Articles

FPGA‐based RO PUF with low overhead and high stability

Ring oscillator physical unclonable functions (RO PUF) promise cheap, efficient, and secure identification and authentication of the chip. However, RO PUF typically has high hardware overhead, and it is difficult to guarantee its stability due to the complex operating environment. In this Letter, the programmable delay lines were utilised to configure the ring oscillator to improve the performance of PUF on FPGA. The proposed structure generates a 16-bit reliable PUF response using only two slices. Experimental results show that the proposed PUF has low hardware overhead, and multiple measurements under a wide range of operating environments demonstrate that it is highly stable.

Secure hardware-entangled field programmable gate arrays

The configuration bitstream is a persistent source of vulnerability in FPGA designs, and thus FPGA vendors have implemented bitstream encryption. A number of attacks on these countermeasures have been demonstrated including direct probing of the configuration storage cells, side-channel attacks on the decryption blocks, and attacks on the scan chain. Thus, we present an FPGA design that never stores the configuration data in the clear, even at the lowest level of the hardware. We deeply hardware entangle the reconfigurable logic and interconnect by one time pad encrypting the bitstream using a PUF response. By leveraging recent work in high performance, high density, high reliability, and low power PUF design, we tightly integrate a PUF bit with every configuration bit. This has significant security benefits including high resistance to probing attacks and unique per-die configuration bitstreams, while only requiring minor modification of the FPGA design. Based on overheads from a PUF implementation in an industrial 65 nm bulk CMOS process, we simulate such an FPGA design and achieve modest overheads in power, area, and performance across multiple security-focused benchmark applications, as well as various MCNC benchmark circuits from a variety of real applications.

HCIC: Hardware-Assisted Control-Flow Integrity Checking

Recently, code reuse attacks (CRAs), such as return-oriented programming (ROP) and jump-oriented programming (JOP), have emerged as a new class of ingenious security threats. Attackers can utilize CRAs to hijack the control flow of programs to perform malicious actions without injecting any codes. Many defenses, classed into software-based and hardware-based, have been proposed. However, software-based methods are difficult to be deployed in practical systems due to high performance overhead. Hardware-based methods can reduce performance overhead but may require extending instruction set architectures (ISAs) and modifying the compiler or suffer the vulnerability of key leakage. To tackle these issues, this paper proposes a new hardware-assisted control flow checking method to resist CRAs with negligible performance overhead without extending ISAs, modifying the compiler or leaking the encryption/decryption key. The key technique involves two control flow checking mechanisms. The first one is the encrypted Hamming distances matching between the physical unclonable function (PUF) response and the return addresses, which prevents attackers from returning between gadgets so long as the PUF response is secret, thus resisting ROP attacks. The second one is the linear encryption/decryption operation (XOR) between the PUF response and the instructions at target addresses of call and jmp instructions to defeat JOP attacks. Advanced return-based full-function reuse attacks will be prevented with the dynamic key-updating method. Experimental evaluations on benchmarks demonstrate that the proposed method introduces negligible 0.95% runtime overhead and 0.78% binary size overhead on average.

Efficient PUF-Based Key Generation in FPGAs Using Per-Device Configuration

Reconfigurable systems often require secret keys to encrypt and decrypt data. Applications requiring high security commonly generate keys based on physical unclonable functions (PUFs), circuits that use random manufacturing variations to produce secret keys that are unique to each device. Implementing PUFs on field-programmable gate arrays (FPGAs) is usually difficult, because the designer has limited control over layout, and each PUF system requires a large area overhead to correct errors in the PUF response bits. In this paper, we extend the state of the art for FPGA-based weak PUFs using a novel methodology of per-device configuration and a new PUF variant derived from the popular FPGA-specific Anderson PUF. The PUF is evaluated using Xilinx XC7Z020 programmable systemon-chips from the Virtex-7 family on Zynq ZedBoard platforms. The design we propose has several advantages over existing work including the Anderson PUF on which it is based. Our design is tunable to minimize the response bias and can be implemented using the common SLICEL components on Xilinx FPGAs. Moreover, the proposed PUF design enables an efficient per-device configuration that reduces bit error rate by over 10× at room temperature and improves response stability by over 2× across all temperatures. We demonstrate that the proposed per-device PUF configuration step leads to roughly 2× savings in area resources for PUFs and error correction as used in key generation.

A Theoretical Model to Link Uniqueness and Min-Entropy for PUF Evaluations

Physical unclonable functions (PUFs) are security primitives that enable the extraction of digital identifiers from electronic devices, based on the inherent silicon process variations between devices which occur during the manufacturing process. Due to the intrinsic and lightweight nature of a PUF, they have been proposed to provide security at a low cost for many applications, in particular for the internet of things (IoT). Many metrics have been proposed to evaluate the security and performance of PUF architectures, two of which are uniqueness and min-entropy. The uniqueness of a PUF response evaluates its ability to differentiate between different physical devices, while the min-entropy estimation is a measure of how much uncertainty the PUF response contains. The min-entropy is a lower-bound of real entropy. When the uniqueness of a PUF design is close to the optimal, it is unclear if this also implies that the design has a significantly high entropy; hence it would be useful to ascertain the minimum uniqueness required to achieve a given entropy. To date, a thorough investigation of the relationship between uniqueness and entropy for PUF designs has not been conducted. In this paper, this relationship between the uniqueness and entropy is explored, and for the first time, to the authors’ knowledge, the relationship between them is modeled. To verify this model, both simulated and hardware-based experimental results are performed, with a test-bed containing 184 Xilinx Artix-7 FPGA based Basys3 boards providing a large data set for granular results. The experimental results demonstrate that the proposed model accurately estimates the relationship between uniqueness and min-entropy, with both the theoretical analysis and software simulations closely matching the experimental results.

Efficient Fuzzy Extractors Based on Ternary Debiasing Method for Biased Physically Unclonable Functions

This paper proposes a new debiasing method and its application to fuzzy extractors (FEs) for stable and efficient extraction of uniform random binary responses from biased physically unclonable functions (PUFs). The proposed method handles PUF responses as ternary responses assuming that an unstable response bit is the third value, and stably extracts uniform random binary responses from them. In this paper, we evaluate the stability and effectiveness of the proposed method via two experiments with simulated and actual responses of latch PUFs. We demonstrate that the proposed method can obtain longer debiased random binary responses than the conventional method. In addition, we apply the debiasing method to the construction of FEs; in an experimental evaluation, we show the advantages of the proposed FE in terms of needed PUF size and authentication success rate. The results show the advantage of the proposed method to other conventional methods. In particular, the needed PUF sizes in the proposed FE were 34%-38% shorter than those in the conventional binary method under the condition that the authentication success rates are sufficient.

PUFmeter a Property Testing Tool for Assessing the Robustness of Physically Unclonable Functions to Machine Learning Attacks

As PUFs become ubiquitous for commercial products (e.g., FPGAs from Xilinx, Altera, and Microsemi), attacks against these primitives are evolving toward more omnipresent and even advanced techniques. Machine learning (ML) attacks, among other non-invasive attacks, are proven to be feasible and cost-effective in the real-world. However, for PUF designers, it still remains an open question whether their countermeasures, or even new designs, are resistant to these types of attacks. Although standard metrics for estimating PUF quality exist, the most common approaches for measuring resistance to ML attacks are empirical. This paper introduces PUFmeter, a new publicly available toolbox consisting of in-house developed algorithms, to provide a firm basis for the robustness assessment of PUFs against ML attacks. To this end, new metrics and notions are reintroduced by PUFmeter to PUF designers and manufacturers. Furthermore, to prepare the PUF input-output pairs adequately before conducting any analysis, PUFmeter involves modules that output the minimum number of measurement repetitions and the upper bound on the noise level affecting the PUF responses.

SHAIP

In this article, we present SHAIP, a secure Hamming distance–based mutual authentication protocol. It allows an unlimited number of authentications by employing an intrinsic Physical Unclonable Function (PUF). PUFs are being increasingly employed for remote authentication of devices. Most of these devices have limited resources. Therefore, the intrinsic PUFs are most suitable for this task as they can be built with little or no modification to the underlying hardware platform. One major drawback of the current authentication schemes is that they expose the PUF response. This makes the intrinsic PUFs, which have a limited number of challenge-response pairs, unusable after a certain number of authentication sessions. Moreover, these schemes are one way in the sense that they only allow one party, the prover, to authenticate herself to the verifier. We propose a symmetric mutual authentication scheme based on secure (privacy-preserving) computation of the Hamming distance between the PUF response from the remote device and reference response stored at the verifier end. This allows both parties to authenticate each other without revealing their respective sets of inputs. We show that our scheme is effective with all state-of-the-art intrinsic PUFs. The proposed scheme is lightweight and does not require any modification to the underlying hardware.

CMOS Optical PUFs Using Noise-Immune Process-Sensitive Photonic Crystals Incorporating Passive Variations for Robustness

This paper introduces a new design methodology for incorporating process-sensitive optical nanostructures in standard CMOS processes to create robust optical physically unclonable functions (PUFs) realized through an electrical-photonic co-design approach. The passive lithographic variations of lower level metal interconnects are exploited to realize resonant photonic crystals on an array of photodetectors to include variations that are robust to noise processes. The chip is realized in a standard 65-nm CMOS process with no additional post-processing. The addition of the structures increases the coefficient of variation by a factor of 3.5 $\times $ compared to only active device variations. This creates extremely robust PUF responses with a native inter-chip Hamming distance (HD) of 49.81% and intra-chip HD of 0.251% with an inter-HD/ intra-HD ratio of 198 $\times $ illustrating the reliability of the design. The native intra-HD can be reduced to 0.06% with 17 mV of thresholding with only 4% of the total combinations discarded. To the best our knowledge, this is also the first demonstration of photonic crystals and an optical PUF in CMOS.

A novel reliable and aging tolerant modified RO PUF for low power application

Ring oscillator (RO) based physical unclonable functions (PUF) is one of the widely used security primitive because of its simple architecture and ease of collecting responses. The oscillation frequency of RO section is used to derive the responses of PUF. The dependency of oscillation frequency on aging and temperature variation causes degradation in the reliability of PUF. Further, the quality factors of PUF depend upon the impact of process variation (PV). In this paper, we used dynamic logic style like feedthrough logic (FTL) in place of conventional static CMOS to design the RO in order to enhance its reliability and the use of FTL increases the impact of PV on RO section. Further, our proposed modified RO PUF architecture is suitable in low power and area constraint application. The quality factors analysis of the proposed modified RO PUF is carried out in 90 nm CMOS technology. Simulation results confirm higher reliability and improved power feature of proposed RO PUF architecture.

Total Ionizing Dose Effects on a Delay-Based Physical Unclonable Function Implemented in FPGAs

Physical Unclonable Functions (PUFs) are hardware security primitives that are increasingly being used for authentication and key generation in ICs and FPGAs. For space systems, they are a promising approach to meet the needs for secure communications at low cost. To this purpose, it is essential to determine if they are reliable in the space radiation environment. In this work we evaluate the Total Ionizing Dose effects on a delay-based PUF implemented in SRAM-FPGA, namely a Ring Oscillator PUF. Several major quality metrics have been used to analyze the evolution of the PUF response with the total ionizing dose. Experimental results demonstrate that total ionizing dose has a perceptible effect on the quality of the PUF response, but it could still be used for space applications by making some appropriate corrections.

Phase Calibrated Ring Oscillator PUF Design and Application

A Ring Oscillator Physical Unclonable Function (RO PUF) is an application-constrained hardware security primitive that can be used for authentication and key generation. PUFs depend on variability during the fabrication process to produce random outputs that are nevertheless stable across multiple measurements. Though industry has a growing need for PUF implementations on Field Programmable Gate Arrays (FPGA) and Application-Specific Integrated Circuits (ASIC), the bit errors in PUF responses become a bottleneck and limit the usage. In this work, we comprehensively evaluate the RO PUF’s stability on FPGAs, and we propose a phase calibration process to improve the stability of RO PUFs. We also make full use of the instability of PUFs to provide a novel solution for authentication. The results show that the bit errors in our PUFs are reduced to less than 1%.

Intrinsic Run-Time Row Hammer PUFs: Leveraging the Row Hammer Effect for Run-Time Cryptography and Improved Security †

Physical Unclonable Functions (PUFs) based on the retention times of the cells of a Dynamic Random Access Memory (DRAM) can be utilised for the implementation of cost-efficient and lightweight cryptographic protocols. However, as recent work has demonstrated, the times needed in order to generate their responses may prohibit their widespread usage. To address this issue, the Row Hammer PUF has been proposed by Schaller et al., which leverages the row hammer effect in DRAM modules to reduce the retention times of their cells and, therefore, significantly speed up the generation times for the responses of PUFs based on these retention times. In this work, we extend the work of Schaller et al. by presenting a run-time accessible implementation of this PUF and by further reducing the time required for the generation of its responses. Additionally, we also provide a more thorough investigation of the effects of temperature variations on the Row Hammer PUF and briefly discuss potential statistical relationships between the cells used to implement it. As our results prove, the Row Hammer PUF could potentially provide an adequate level of security for Commercial Off-The-Shelf (COTS) devices, if its dependency on temperature is mitigated, and, may therefore, be commercially adopted in the near future.

Spatial Correlation Analysis on Physical Unclonable Functions

The evaluation of the quality of physical unclonable functions (PUFs) is still under research. Most state-of-the-art metrics are found to measure only bias, while correlations, e.g., within the PUF response of a single device, remain unnoticed. In this paper, we introduce spatial autocorrelation analysis (SPACA), which is used in other fields of research, as a method to reveal correlations in the response of single-challenge PUFs. The presented statistics—Moran’s I, Geary’s c, and Join Count statistic—can be used to test the quality of an implementation using a set of sample devices as well as monitor ongoing production. Their results are also important for selecting an appropriate post-processing of the raw PUF response. Experiments on data sets from three different PUF implementations on field-programmable gate array and application-specific integrated circuit using SPACA show the capabilities of the introduced statistics. An efficient implementation of SPACA in MATLAB was developed to conduct the experiments. We discuss how SPACA can be used in practical testing and suggest to consider SPACA for a future test suite for PUFs.

Pitfall of the Strongest Cells in Static Random Access Memory Physical Unclonable Functions.

Static Random Access Memory (SRAM) Physical Unclonable Functions (PUFs) are some of the most popular PUFs that provide a highly-secured solution for secret key storage. Given that PUF responses are noisy, the key reconstruction must use error correcting code (ECC) to reduce the noise. Repetition code is widely used in resource constrained systems as it is concise and lightweight, however, research has shown that repetition codes can lead to information leakage. In this paper we found that the strongest cell distribution in a SRAM array may leak information of the responses of SRAM PUF when the repetition code is directly applied. Experimentally, on an ASIC platform with the HHGRACE 0.13 μm process, we recovered 8.3% of the measured response using the strongest cells revealed by the helper data, and we finally obtained a clone response 79% similar to weak response using the public helper data. We therefore propose Error Resistant Fuzzy Extractor (ERFE), a 4-bit error tolerant fuzzy extractor, that extracts the value of the sum of the responses as a unique key and reduces the failure rate to 1.8 × 10−8 with 256 bit entropy.

Eliminating Leakage in Reverse Fuzzy Extractors

In recent years, physically unclonable functions (PUFs) have been proposed as a promising building block for key storage and device authentication. PUFs are physical systems, and as such, their responses are inherently noisy, precluding a straightforward derivation of cryptographic key material from raw PUF measurements. To overcome this drawback, fuzzy extractors are used to eliminate the noise and guarantee robust outputs. A special type is reverse fuzzy extractors, shifting the computational load of error correction toward a computationally powerful verifier. However, the reverse fuzzy extractor reveals error patterns to any eavesdropper, which may cause privacy issues (due to a systematic drift of the PUF responses, the error pattern is linkable to the identity) and even security problems (if the noise is data-dependent). In this paper, we quantify the issue of leakage due to asymmetry of noise, leveraging the binary asymmetric channel (BAC) model. We further propose to concatenate two BACs to form a symmetric channel, as a solution that is able to eliminate such noise. Finally, we propose a modified reverse fuzzy extractor that does not leak via the error patterns even in the case of systematic drift of the PUF responses.

Methods for Estimating the Convergence of Inter-Chip Min-Entropy of SRAM PUFs

For cryptographic applications based on physical unclonable functions (PUFs), it is very important to estimate the entropy of PUF responses accurately. The upper bound of the entropy estimated by compression algorithms, such as context-tree weighting, is too loose, while the lower bound estimated by the min-entropy calculation is too conservative, especially when the sample size is small. The actual min-entropy is between these bounds but is difficult to estimate accurately. In this paper, two models are proposed to estimate the convergence of the inter-chip min-entropy of static random-access memory (SRAM) PUFs. The basic idea is to find the relation between the expectation of the estimation result and the tested sample size, and then predict the convergence of the min-entropy. Furthermore, an improved Von Neumann extractor is used to increase the entropy per bit while retaining as many responses as possible for error correction. The experimental results demonstrate that the prediction error of the proposed estimation methods is less than 0.01/bit for the tested SRAM chips, and the improved Von Neumann extractor can reduce the number of required responses by approximately 11/16, the amount of helper data by 2/3, and the number of masks by 3/8 compared with the original method.

A Combined Optimization-Theoretic and Side- Channel Approach for Attacking Strong Physical Unclonable Functions

The promise of strong physical unclonable functions (PUF) is to utilize the manufacturing variations of circuit elements to produce an independent and unpredictable response to any input challenge vector. Attacks on PUFs that predict the responses to input challenge vectors offer an interesting research problem. An attacking approach based on the optimization theory and side-channel information is proposed where we estimate the manufacturing variations of the circuit elements and predict the PUF’s responses to challenge vectors whose actual responses are not known. We apply this attacking approach on some popular PUF designs, including the Arbiter PUFs, the Memristor Crossbar PUFs, and the XOR Arbiter PUFs. Simulations show a substantial reduction in attack complexity compared with previously proposed machine-learning (ML)-based attacks: we achieve an average reduction of 66% in attack time compared with the ML approach. Despite some overhead, our approach is also applicable when the PUF responses are noisy.

ACRO-PUF: A Low-power, Reliable and Aging-Resilient Current Starved Inverter-Based Ring Oscillator Physical Unclonable Function

Ring oscillator (RO)-based physical unclonable function (PUF) is an emerging hardware security primitive but its response reproducibility is susceptible to changes in operating conditions and device aging. Present solutions to increase RO PUF reliability either incur large hardware overhead or require sophisticated RO selection algorithm. This paper exploits the optimal biasing of current starved (CS) inverter for the design of RO PUF with very high reliability against both temperature and voltage variations. With two additional transistors, the CS inverter can be adaptively biased at idle time and in active mode to significantly reduce the overall stress, making the proposed CS RO PUF robust against both environmental condition variations and aging. Without using error correction code, the reliability is further improved by a low-cost proximity detector circuit with a small sacrifice on challenge-response pair space. The correlation between successive RO pairs of different input challenges is also broken by an irregular clocking of the linear feedback shift register used to encipher the input challenges. Based on Monte Carlo simulation in TSMC 40-nm CMOS process, the reliability of native PUF responses has been raised substantially from 89.78% for the regular RO PUF to 95.88% for the proposed CS RO PUF over a broad temperature range of -40°C to 120 °C and ± 20% supply variation. With the proximity detector, the proposed Aging-resistant Current-starved RO (ACRO) PUF can attain 100% reliability statistically by discarding 34.47% fewer challenge-response pairs than the regular RO PUF. It is also ~3.7x more aging resilient than existing aging-resilient RO PUFs with ~2.38x lower power dissipation.

안전한 PUF 응답 전송을 위한 노이즈 삽입 및 복구 알고리즘 하드웨어 설계

안전한 PUF 응답 전송을 위한 노이즈 삽입 및 복구 알고리즘 하드웨어 설계