Physical Unclonable Function Circuit Research Articles

A lightweight dual-link accelerated authentication protocol based on NLFSR-XOR APUF

Physical Unclonable Function (PUF) circuits, as a lightweight hardware security primitive, can provide reliable authentication for resource-constrained Internet of Things (IoT) devices. However, in real-time environments and systems, authentication of embedded devices has strict requirements on resources and low latency. Therefore, this paper proposes a lightweight dual-link accelerated authentication protocol design based on NLFSR-XOR APUF, through the study of Non-Linear Feedback Shift Registers (NLFSR) and XOR APUF circuits. First, the scheme utilizes the symmetric path delay deviation characteristics of APUF and the complexity of NLFSR state transitions to form a nonlinear output function that changes with the challenge signal. Then, a lightweight and attack-resistant authentication protocol is established by combining the random probability of shuffling array bits with the XOR confusion mechanism. Finally, the advantages of GPU parallel computing and AES T-table reconfiguration scheme are used to achieve an accelerated and side-channel attack-resistant authentication protocol. Experimental results show that the PUF circuit can effectively resist various modeling attacks, including logistic regression (LR), artificial neural network (ANN), and support vector machine (SVM). The security of the protocol has been formally verified, and the prototype has been implemented on the Xilinx xc100T development board, effectively resisting deception attacks, physical attacks, and modeling attacks. The protocol's area overhead in terms of LUT and encryption time is reduced by 58.6 % and 67.8 %, respectively, compared to similar protocols.

Data-dependent half-select free GSRAM cell with word line write-assist and built-in read buffer schemes for use in PUFs-based IoT devices

In this study, a static-RAM cell using the Gnr-GDI method is proposed as a weak-type physical unclonable function (PUF) circuit to generate a unique and stable binary output for secure IoT devices. Regarding the memory level, a suitable combination of dynamic body bias, stacked networks, and multi-Vth techniques has been used in the architecture of asymmetric cell-structure inverters as a latch section to reduce power consumption and improve hardware efficiency. In addition, the logic styles of virtual ground and power gating based on word and BL data lines and a tri-state buffer structure have been used to extend the write VTC and improve read stability, respectively. From the perspective of PUF performance, the body of the latch section can form skewed VTCs based on the setting of critical parameters in GnrFET technology to achieve an efficient PUF circuit design.At the memory performance level, the Monte Carlo (MC) method-based results confirm the reasonable performance of the proposed structure in terms of static noise margin (SNM) and hardware efficiency, such as 53 % delay and 72 % energy-delay product (EDP) parameters, compared with the 6 T SRAM structure in a similar 16 nm GnrFET technology. In addition, in terms of the performance as a PUF circuit, the simulation results demonstrate the superiority of the proposed cell in terms of energy consumption, BER, response time, uniqueness, and stability under non-technological variation conditions of temperature and supply voltage. The outstanding performance results of the figure of merits (FoMs), CEQM, and UR2, which are composed of variability, energy, reliability, and layout-level factors, indicate the suitability of the proposed memory architecture for use in both the memory and PUF modes.Furthermore, to investigate the application level, memory structure has been used to store fingerprint images as PUF data using a hardware algorithm. The results of the proposed comprehensive FoM, which is based on the simultaneous consideration of circuit level and quality parameters, indicate that the proposed memory scheme in a bit-interleaved architecture-compatible design can be introduced as a high-performance candidate for generating and storing unique binary data in PUF-based IoT platforms.

T2S-MAKEP and T2T-MAKEP: A PUF-based Mutual Authentication and Key Exchange Protocol for IoT devices

Nowadays, more constrained devices are becoming connected, building an extensive Internet of Things (IoT) network, but suffering from many security issues. In particular, authentication has become a severe research challenge for IoT systems. Furthermore, confidentiality, integrity, and availability are considered the core underpinnings of information security in general. Unfortunately, deploying conventional authentication protocols for IoT devices in practice is challenging for two main reasons. First, IoT devices have limited memory capacity, processing power, and energy resources. Second, these protocols store secret keys in the IoT devices’ volatile memory, making them vulnerable to physical attacks. Luckily, Physical Unclonable Functions (PUF) has emerged as promising low-cost security primitive. A PUF eliminates the need to store secret keys in device memory, making it a potential alternative to deploying more secure and low-cost authentication protocol schemes for IoT systems. Thing-to-Thing (T2T) or direct connection between IoT devices represents a promising technique to enable things to communicate directly without the need for a trusted third party. This paper proposes two novel lightweight Mutual Authentication and Key Exchange Protocols (MAKEP) for IoT devices using PUF. The first scheme, called T2S-MAKEP, ensures secure communication for Thing-to-Server (T2S). The second, called T2T-MAKEP, allows two endpoints of resource-constrained IoT devices, each with an embedded PUF circuit, to communicate securely. Both proposed protocols, T2T-MAKEP and T2S-MAKEP, allow for robust authentication without storing any information on the device’s memory and simultaneously establish the session key exchange. Our proposed protocols have been verified and validated using the automatic security analysis checker, Verifpal.

Low-overhead XOR Multi-PUF against machine learning attacks

Physical unclonable functions (PUF) have been a hot research topic in hardware security in recent years. Still, most of the research has not focused on the design of balancing its resistance to machine learning attacks with resources. Therefore, in this paper, a new low-overhead XOR Multi-PUF design is proposed, which achieves the response of outputting different modes of PUFs with configurable bits to change the number of delays and inverters inside the circuit, completing the PUF design with less hardware overhead. It also introduces an input challenge obfuscation mechanism to improve its resistance to machine learning attacks. In this paper, the proposed PUF circuit design is verified on FPGA boards and good performance metrics are obtained. The design has more challenge-response pairs (CRPs) and less hardware overhead than existing PUF low-overhead designs, improving resistance to machine learning attacks.

Quality of Security Guarantees for and with Physical Unclonable Functions and Biometric Secrecy Systems.

Unique digital circuit outputs, considered as physical unclonable function (PUF) circuit outputs, can facilitate a secure and reliable secret key agreement. To tackle noise and high correlations between the PUF circuit outputs, transform coding methods combined with scalar quantizers are typically applied to extract the uncorrelated bit sequences reliably. In this paper, we create realistic models for these transformed outputs by fitting truncated distributions to them. We also show that the state-of-the-art models are inadequate to guarantee a target reliability level for all PUF outputs, which also means that secrecy cannot be guaranteed. Therefore, we introduce a quality of security parameter to control the percentage of the PUF circuit outputs for which a target security level can be guaranteed. By applying the finite-length information theory results to a public ring oscillator output dataset, we illustrate that security guarantees can be provided for each bit extracted from any PUF device by eliminating only a small subset of PUF circuit outputs. Furthermore, we conversely show that it is not possible to provide reliability or security guarantees without eliminating any PUF circuit output. Our holistic methods and analyses can be applied to any PUF type, as well as any biometric secrecy system, with continuous-valued outputs to extract secret keys with low hardware complexity.

Physically non-cloneable arbiter -type function with non-linear path pairs

Physically unclonable functions (PUFs) are basic physical cryptographical primitives, providing to solve tasks such as unclonable identification, digital device authentication and copyright authentication, true random sequence generation, etc. The major features of PUFs are stability, unpredictability and irreproducibility, due to uncontrollable random variations of distinctive features of the raw materials and technological processes used during their manufacturing. Generally, PUF are digital circuits that extract such variations and convert them into a binary format, which applied for further use. Among the variety of PUF types, an Arbiter PUF (APUF) is distinguished, which is a digital circuit with N-bit challenge input and single output for one-bit response generation. The functionality of APUF is based on comparison of transition time of two copies of the test signal along a pair of configurable paths, selected by the challenge value CH from a set of 2N all possible pairs. The result of the comparison is the binary value of the response. The set of all challenge-response pairs is a random, unpredictable and irreproducible in the cases of implementation of cloned PUF circuits both on single and/or on another chips, also using different technologies. This article presents a new approach to the synthesis of the APUF circuits, based on the permutation network elements, which allow to construct the nonlinear structures of pair of paths. This implies the potential complication of building an APUF model to attack its implemented instances. This article presents new schematic solutions for the synthesis of APUF circuits. Also, the main characteristics of the proposed APUF circuits implemented on the Xilinx Zynq-7000 FPGA is analyzed.

Dynamic self-test scheme and authentication protocol for improving robustness of strong PUF

In the realm of IoT applications, where resources are limited, physical unclonable functions (PUFs) have emerged as a promising encryption strategy due to their lightweight and high-security. While several PUFs have been proposed, there is still a need to balance low-cost and high security given the constraints of hardware resources. This paper presents a PUF design based on sub-threshold current arrays that offers high resource utilization. To improve the robustness of PUF response, a dynamic control and self-test scheme is proposed. Additionally, a high-efficiency authentication protocol is developed to enhance the utilization of CRPs. Even if an unstable response is generated, the proposed protocol considers it to be authenticated successfully as long as the degree of stability of the response is within a specific range. The PUF circuit occupies only 377.4 nm2 and achieves good uniqueness and stability with a bit error rate (BER) of 0.45% per 10 °C over a temperature range of −40 °C to 80 °C.

A 325F 2 Physical Unclonable Function Based on Contact Failure Probability With Bit Error Rate < 0.43 ppm After Preselection With 0.0177% Discard Ratio

Preselection methods in which unstable bitcells are discarded are widely used to enhance the stability of the physical unclonable function (PUF). If the discard range of the preselection is too narrow, all unstable bitcells cannot be discarded, whereas, if the discard range is too wide, the PUF circuit area increases because the number of redundant bitcells should increase. Moreover, the discard range of most previous PUFs is not determined by theoretical analysis but rather by repeated measurements, which requires a long test time and cannot determine the accurate discard range to guarantee the PUF stability. This article demonstrates an efficient preselection method to determine the discard range through a theoretical analysis of the PUF entropy source for the PUF based on contact failure probability (contact PUF). After this preselection with the discard ratio of 0.0177%, no PUF responses changed among 2 367 040 bits from 1138 chips, i.e., bit error rate <inline-formula> <tex-math notation="LaTeX">$&lt;$</tex-math> </inline-formula>0.43 ppm, in seven harsh environmental tests regulated by the Joint Electron Device Engineering Council (JEDEC) standard. The proposed preselection method also enables the contact PUF to be implemented in a small area due to the low discard ratio. A small-area design methodology of contact PUF bitcells is also proposed. The PUF bitcell area per bit is 325<inline-formula> <tex-math notation="LaTeX">$F^{2}$</tex-math> </inline-formula>, the smallest area compared to previous PUFs. The contact PUF with the proposed preselection applied is fabricated in 100-nm CMOS technology. It achieves 0.4999 of uniqueness and 0.9942 of Shannon entropy and passes all applicable randomness tests stipulated by the National Institute of Standards and Technology (NIST) SP800-22.

Stabilizing Techniques for Secure On-chip Key Generation Based on RO-PUF

Based on intrinsic physical characteristics of devices, Physically Unclonable Functions (PUFs) provide the high reliability while maintaining the sufficient uniqueness. However, in the practical implementation based on PUFs, the extracted bit-string normally exhibits the unavoidable small fluctuation. Hence, PUFs can be used for the application of chip identification, but not suitable for the application that strictly requires an exact generated number. In this work, we propose several techniques to stabilize the generated value based on the existing Ring Oscillator (RO)-PUF circuit so that the stable unique number can be directly used for high-profile hardware security applications. In detail, we design a specialized on-chip key generation circuit that repeatedly samples the RO frequency values for statistical analysis and dynamically phases out the unstable bits, resulting in a unique and stable output bit-string. The experiments are conducted for the actual data measured from Xilinx Artix-7 FPGA devices. The generated key is proven to be relatively stable and can be readily used for the emerging security applications.

A greedy algorithm based Compensation Circuit for Optimizing the Output Statistics of APUF

Physical unclonable function (PUF) can reduce the risk of password leakage of smart connected devices, and has broad application prospects in the field of information security. However, in actual implementation, the designed PUF often deviates greatly due to a lack of experience in using the FPGA platform. Therefore, this paper proposes an APUF adaptive compensation method based on a greedy algorithm. This method can modify the delay by changing the internal transmission path, thereby reducing the skew between APUF paths. First, to enhance the randomness of the APUF output, a compensation circuit with equal delay on the symmetric path of APUF is constructed in a differential manner. Then, the local solution is used to construct the global solution by using the greedy algorithm, which further improves the circuit regulation speed. Finally, the proposed method is implemented on FPGA, and the effectiveness of the method is verified by analyzing the statistical characteristics of the output. The experimental results show that the randomness (49.56%), uniqueness (49.08%), and reliability (95.78%) of APUF are close to the ideal values after using the adaptive compensation method. In addition, when implemented on different FPGA platforms and different chip locations, the average randomness of the PUF circuit is 49.46%. Therefore, the method is highly applicable and can be applied to all the same types of FPGA platforms without subsequent adjustments.

A BER-Suppressed PUF With an Amplification of Process Mismatch Effect in an Oscillator Collapse Topology

The physically unclonable function (PUF) has been implemented with circuits that perform amplification of randomly given small process mismatch by using an explicit amplifier or by making a signal path repeatedly experience the same delay skew in an oscillator. Though the amplifier approach provides a fast response, it is vulnerable to noise at the first stage of amplification. On the other hand, the oscillator-based scheme requires a longer time to develop a digital output while achieving good noise immunity. This article proposes a PUF circuit exploiting a hybrid architecture, which combines a process skew amplification scheme in an oscillator collapse topology. The proposed scheme compensates for the drawbacks of the two approaches while achieving merits of them, i.e., high sensitivity to process variation and good immunity to noise. The supply rails of an even-stage ring oscillator (RO) are alternately fed from a diode-based threshold-sampling block. An IC with an array of 128 PUF cells is fabricated in 40-nm CMOS, showing a native bit error rate (BER) of 0.027%. Processing of 7-b temporal majority voting (TMV7) with a 3.64% masking demonstrates an error-free operation in a nominal condition. It shows a BER of 0.0019% in the worst condition under a voltage range of 0.7–1.4 V and a temperature range of −40 °C to 125 °C.

A low-overhead PUF for anti-clone attack of RFID tags

Physically Unclonable Function (PUF) is one of the important research techniques for anti-cloning attacks in Radio Frequency Identification (RFID) tags security. But in RFID tags, there are not quite a few resources left for PUF. Therefore, this paper designs a new lightweight reconfigurable XOR RO PUF, which can simultaneously switch the internal delay of each inverter and the number of ring oscillator stages, increase the delay complexity with less hardware overhead, and generate more multiple authentication keys. In this paper, the proposed PUF circuit design is verified and good performance indicators are obtained. By comparison with the existing PUF low-overhead design, this design has more challenge/response pairs (CRPs) and less hardware overhead without reducing the uniformity, randomness, uniqueness and reliability of the PUF.

Preselection Methods to Achieve Very Low BER in SRAM-Based PUFs—A Tutorial

The most prevalent industrial PUFs (physical unclonable functions) utilize SRAM-based designs. Bit stability is one of the fundamental problems in PUF design. PUF circuits, which rely on silicon manufacturing mismatches to produce a random key, are vulnerable to cases where the mismatch is insufficient and noise affects the PUF response, rendering it unstable. This brief provides a tutorial about SRAM-based PUFs stable bits preselection, utilizing an embedded tilt test. This method is more efficient than existing error correction codes in terms of power, area and latency. During the test, external, controlled mismatch, tilts the PUF cells against their manufactured mismatch and cells that retain their response are considered stable. In this tutorial, the preselection method is explained, implementation examples are presented, and a method to further exploit the test to obtain more uncorrelated stable bits from the existing PUF structure is introduced.

A New Security Boundary of Component Differentially Challenged XOR Pufs Against Machine Learning Modeling Attacks

Physical Unclonable Functions (PUFs) are promising security primitives for resource-constrained network nodes. The XOR Arbiter PUF (XOR PUF or XPUF) is an intensively studied PUF invented to improve the security of the Arbiter PUF, probably the most lightweight delay-based PUF. Recently, highly powerful machine learning attack methods were discovered and were able to easily break large-sized XPUFs, which were highly secure against earlier machine learning attack methods. Component-differentially-challenged XPUFs (CDC-XPUFs) are XPUFs with different component PUFs receiving different challenges. Studies showed they were much more secure against machine learning attacks than the conventional XPUFs, whose component PUFs receive the same challenge. But these studies were all based on earlier machine learning attack methods, and hence it is not clear if CDC-XPUFs can remain secure under the recently discovered powerful attack methods. In this paper, the two current most powerful two machine learning methods for attacking XPUFs are adapted by fine-tuning the parameters of the two methods for CDCXPUFs. Attack experiments using both simulated PUF data and silicon data generated from PUFs implemented on field-programmable gate array (FPGA) were carried out, and the experimental results showed that some previously secure CDC-XPUFs of certain circuit parameter values are no longer secure under the adapted new attack methods, while many more CDC-XPUFs of other circuit parameter values remain secure. Thus, our experimental attack study has re-defined the boundary between the secure region and the insecure region of the PUF circuit parameter space, providing PUF manufacturers and IoT security application developers with valuable information in choosing PUFs with secure parameter values.

A Novel RFID Authentication Protocol Based on Reconfigurable RRAM PUF.

Radio frequency identification technology (RFID) has empowered a wide variety of automation industries. Aiming at the current light-weight RFID encryption scheme with limited information protection methods, combined with the physical unclonable function (PUF) composed of resistive random access memory (RRAM), a new type of high-efficiency reconfigurable strong PUF circuit structure is proposed in this paper. Experimental results show that the proposed PUF shows an almost ideal value (50%) of inter-chip hamming distance (HD) (µ/ = 0.5001/0.0340) among 1000 PUF keys, and intra-chip HD results are very close to the ideal value (0). The bit error rate (BER) is as low as across one million challenges. Based on the RRAM PUF, we propose and implement a light weight RFID authentication protocol. By virtue of RRAM’s model ability, the protocol replaces the One-way Hash Function with a response chain mutual encryption algorithm. The results of test and analysis show that the protocol can effectively resist multiple threats such as physical attacks, replay attacks, tracking attacks and asynchronous attacks, and has good stability. At the same time, based on RRAM’s unique resistance variability, PUF also has the advantage of being reconfigurable, providing good security for RFID tags.

Design of Lightweight and Configurable Strong Physical Unclonable Function

<p indent="0mm">To solve the problem that the physical unclonable function (PUF) structure is simple and vulnerable to modeling attacks, a strong PUF anti-attack obfuscation design based on linear feedback shift register (LFSR) is proposed. First, a fixed structure LFSR is used as a pseudo-random number generator to provide a random selection signal for the obfuscation logic. Then, a dynamic LFSR with multiple feedback polynomials is used as the obfuscation logic to obfuscate origin challenges. Finally, obfuscated challenges are loaded into the embedded PUF circuit so that the attacker cannot obtain real challenges. It improves the resistance of the PUF to modeling attacks. The proposed design is simulated by Python and FPGA. Experiments on the collected dataset show that the proposed PUF has ideal uniformity (49.8%) and uniqueness (49.9%) and keeps the same reliability. It has simple architecture and low hardware overhead and can resist a variety of modeling attacks including machine learning and deep learning.

Survey on the benefits of using memristors for PUFs

This paper reviews memristive PUFs (Physical Unclonable Functions) reported in the literature. The paper explains the motivation for using memristor technology for implementing PUFs. It focuses on PUFs’ applications, sizes, analysis, and physical variations. In addition, the paper presents the number of samples generated using Monte Carlo simulation for evaluating the PUF circuits. This paper also describes the protocols, functionality, and methodologies proposed in the memristive PUF literature. Although memristive PUFs are not commercialized yet, there is a high expectation of exploiting the memristors as fundamental elements in the next generation of hardware security primitives (e.g. PUF) due to their unique characteristics such as forming process, temporal drift, nonlinearity, bidirectionality, nonvolatility and model complexity. There have been some survey papers on memristor PUFs in the past, however, the field has continued to develop so a comprehensive survey including recent publications seemed in order at this time. Lately, memristor technology improvement has accelerated, therefore creating a need for an updated survey of the applications of memristors for PUFs.

A Conditionally Chaotic Physically Unclonable Function Design Framework with High Reliability

Physically Unclonable Function (PUF) circuits are promising low-overhead hardware security primitives, but are often gravely susceptible to machine learning–based modeling attacks. Recently, chaotic PUF circuits have been proposed that show greater robustness to modeling attacks. However, they often suffer from unacceptable overhead, and their analog components are susceptible to low reliability. In this article, we propose the concept of a conditionally chaotic PUF that enhances the reliability of the analog components of a chaotic PUF circuit to a level at par with their digital counterparts. A conditionally chaotic PUF has two modes of operation: bistable and chaotic , and switching between these two modes is conveniently achieved by setting a mode-control bit (at a secret position) in an applied input challenge. We exemplify our PUF design framework for two different PUF variants—the CMOS Arbiter PUF and a previously proposed hybrid CMOS-memristor PUF, combined with a hardware realization of the Lorenz system as the chaotic component. Through detailed circuit simulation and modeling attack experiments, we demonstrate that the proposed PUF circuits are highly robust to modeling and cryptanalytic attacks, without degrading the reliability of the original PUF that was combined with the chaotic circuit, and incurs acceptable hardware footprint.

An Efficient Design of Anderson PUF by Utilization of the Xilinx Primitives in the SLICEM

Physical unclonable functions (PUFs) are known as one of the most recent promising technologies for cryptographic key generation. A PUF circuit is designed in such a way to produce random digits based on true-random and uncontrollable variations during the integrated circuits (IC) manufacturing process. The response of PUF can be used as a unique identity for the device where the PUF is embedded in it. Field-programmable gate arrays (FPGAs) are usually considered as one of the first choices for implementing PUFs. This paper proposes a novel FPGA-derived Anderson PUF by optimizing all elements located in one configurable logic blocks (CLBs). The experimental results on Spartan-6 family Xilinx XC6SLX9 FPGAs show that the proposed architecture improves the PUF's uniformity, uniqueness, and reliability to 49.41%, 50.89%, and 91.25%, respectively. Furthermore, the proposed structure increases the complexity and unpredictability of the PUF while decreases the hardware area overhead.

A Physical Unclonable Function Using a Configurable Tristate Hybrid Scheme With Non-Volatile Memory

The physical unclonable function (PUF) is a promising low-cost hardware security primitive. Recent advances in nanotechnology have provided new opportunities for nanoscale PUF circuits. The resistive random access memory (RRAM) is extensively used in nanoscale circuits due to its low cost, non-volatility and easy integration with CMOS. This paper proposes a novel tristate hybrid PUF (TH-PUF) design based on a one-transistor-one-RRAM (1T1R) cell; this cell can be configured into two weak PUFs and a strong PUF using few control signals. To assess the proposed PUF design, a compact RRAM model at UMC 65 nm technology is employed. Simulation results show that the proposed TH-PUF achieves good uniqueness, reliability as well as a higher gate usability compared with an entire CMOS PUFs. The number of challenge response pairs (CRPs) of the proposed TH-PUF is larger than other RRAM-based PUFs. Moreover, the TH-PUF is more resistant to a modeling machine learning attack than traditional PUF designs.