Abstract
Physical unclonable functions (PUFs) are known as one of the most recent promising technologies for cryptographic key generation. A PUF circuit is designed in such a way to produce random digits based on true-random and uncontrollable variations during the integrated circuits (IC) manufacturing process. The response of PUF can be used as a unique identity for the device where the PUF is embedded in it. Field-programmable gate arrays (FPGAs) are usually considered as one of the first choices for implementing PUFs. This paper proposes a novel FPGA-derived Anderson PUF by optimizing all elements located in one configurable logic blocks (CLBs). The experimental results on Spartan-6 family Xilinx XC6SLX9 FPGAs show that the proposed architecture improves the PUF's uniformity, uniqueness, and reliability to 49.41%, 50.89%, and 91.25%, respectively. Furthermore, the proposed structure increases the complexity and unpredictability of the PUF while decreases the hardware area overhead.
Highlights
Physical security has become a significant concern in security applications related to cyber-physical systems in recent years
Concerning the different physical characteristics of this kind of Field-programmable gate arrays (FPGAs) that are 45 nm FPGAs compared with the Virtex-5 that is used in the original Anderson Physical unclonable functions (PUFs) is different, regard to the point we proposed a new design that can address the required needs
Anderson PUF is an appropriate choice to be implemented on the hardware with the minimum required resources
Summary
Physical security has become a significant concern in security applications related to cyber-physical systems in recent years. Since the manufacturing process variations are entirely random, the PUFs responses are usually hard to predict [4]. These unique features of PUF make it very suitable for security applications such as key generation, authentication, and identification [5]–[9]. The critical point to generating random digits through Anderson PUF is to generate a glitch of sufficient length to be created by many interlocking multiplexers called carry chains located in the CLB. This glitch inputs to a flip-flop and enables its preset.
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