Physical Unclonable Function Design Research Articles

Lightweight Configurable Ring Oscillator PUF Based on RRAM/CMOS Hybrid Circuits

Physical unclonable function (PUF) is a lightweight security primitive for energy constrained digital systems. As an enhanced design of conventional ring oscillator (RO) PUFs, configurable ring oscillator (CRO) PUFs improve the uniqueness and reliability compared with the conventional RO PUF designs. In typical CRO PUF designs, multiplexers (MUXs) are utilized as configurable components. In this paper, a hybrid nano-scale CRO ( $hn$ -CRO) PUF is proposed. The configurable components of the proposed $hn$ -CRO PUF are implemented by RRAMs. The delay elements are based on CMOS inverters. Compared with traditional CRO PUF designs, the proposed $hn$ -CRO PUF is cost-efficient in terms of circuit density and gate per challenge response pair (CRP) bit. To validate the proposed $hn$ -CRO PUF, the Monte Carlo simulation results of a compact RRAM model under UMC 65 nm technology are presented. The results show that the proposed $hn$ -CRO PUF has a good uniqueness and low hardware consumption compared with the previous works.

Homogeneous and Heterogeneous Feed-Forward XOR Physical Unclonable Functions

Physical unclonable functions (PUFs) are hardware security primitives that are used for device authentication and cryptographic key generation. Standard XOR PUFs typically contain multiple standard arbiter PUFs as components, and are more secure than standard arbiter PUFs or feed-forward (FF) arbiter PUFs (FF PUFs). This paper proposes design of feed-forward XOR PUFs (FFXOR PUFs) where each component PUF is a FF PUF. Various homogeneous and heterogeneous FFXOR PUFs are presented and evaluated in terms of four fundamental properties of PUFs: uniqueness, attack-resistance, reliability and randomness. Certain key issues pertaining to XOR PUFs such as their vulnerability to machine learning attacks and instability in responses are investigated. Other important challenges like the lack of uniqueness in FF PUFs and the asymmetry in FPGA arbiter PUFs are addressed and it is shown that FFXOR PUFs can naturally overcome these problems. It is shown that heterogeneous FFXOR PUFs (i.e., FFXOR PUFs with non-identical components) can be resilient to state-of-the-art machine learning attacks. We also present systematic reliability analysis of FFXOR PUFs and demonstrate that soft-response thresholding can be used as an effective countermeasure to overcome the degraded reliability bottleneck. Observations from simulations are further verified through hardware implementation of 64-bit FFXOR PUFs on Xilinx Artix-7 FPGA.

Practical Experiments to Evaluate Quality Metrics of MRAM-Based Physical Unclonable Functions

Process variations in the manufacturing of digital circuits can be leveraged to design Physical Unclonable Functions (PUFs) that are extensively employed in hardware-based security. Different PUFs based on Magnetic Random-Access-Memory (MRAM) devices have been studied and proposed in the literature. However, most of these studies have been simulation-based, which do not fully capture the physical reality. We present experimental results on a PUF implemented on dies fabricated with a type of the MRAM technology namely Thermally-Assisted-Switching MRAM (TAS-MRAM). To the best of our knowledge, this is the first experimental validation of a TAS-MRAM-based PUF. We demonstrate how voltage values used for writing in the TAS-MRAM cells can make stochastic behaviors required for PUF design. The analysis of the obtained results provides some preliminary findings on the practical application of TAS-MRAM-based PUFs in authentication protocols. Besides, the results show that for key-generation protocols, one of the standard error correction methods should be employed if the proposed PUF is used.

A Spintronics Memory PUF for Resilience Against Cloning Counterfeit

With the widespread use of electronic devices in embedding or processing sensitive information, new hardware security primitives have emerged to improve the shortcomings of traditional secure data storage. One of these solutions, the physically unclonable function (PUF), which is widely used for authentication and cryptography applications, extracts the unique and unclonable value from the circuit physical properties. However, a cloning attack on memory-based PUF has been demonstrated from the circuit back-side tampering, questioning its unclonable property and opening counterfeiting vulnerability in an untrusted supply chain. Spin transfer torque-magnetic random-access memory (STT-MRAM) is a promising technology due to its nonvolatility, scalability, and CMOS compatibility, therefore envisioned to be used in many embedded secure devices. In this paper, we reveal the vulnerability of existing STT-MRAM PUF solutions to back-side attacks by modeling different levels of tampering and their impact at electrical and logical levels. We propose a tamper resilient methodology for the STT-MRAM PUF design based on its switching properties. The resilience of the proposed solution to different levels of tampering and a 100% detection are confirmed with simulation results.

A Wide-Range Variation-Resilient Physically Unclonable Function in 28 nm

This article presents a wide-range, variation-resilient physically unclonable function (PUF) to provide a reliable security primitive solution. The proposed ring oscillator-based PUF employs several stabilization techniques to maintain robustness under environmental variations. The proposed PUF design uses a delay cell topology with an adjusted signal slope to amplify the impact of device variability on delay mismatch. Moreover, an online calibration system that extracts in situ PUF delay information and re-configures stage interconnects is employed to further enlarge frequency mismatch and improve stability. Measurement results from a prototype fabricated in a 28-nm CMOS technology show that the proposed PUF design achieves a highly stable performance over a wide range of operating conditions, with a worst case bit error rate (BER) of 0.55% across 0.4–1.3 V and −40 to 125 °C. The measured BER sensitivities to supply voltage (0.0546%/0.1 V) and temperature (0.0052%/10 °C) demonstrate the stability improvements of 2.38 and 28.84 times, respectively, when compared with the state-of-the-art results.

Use of Thermistor Temperature Sensors for Cyber-Physical System Security.

The last few decades have seen a large proliferation in the prevalence of cyber-physical systems. This has been especially highlighted by the explosive growth in the number of Internet of Things (IoT) devices. Unfortunately, the increasing prevalence of these devices has begun to draw the attention of malicious entities which exploit them for their own gain. What makes these devices especially attractive is the various resource constraints present in these devices that make it difficult to add standard security features. Therefore, one intriguing research direction is creating security solutions out of already present components such as sensors. Physically Unclonable Functions (PUFs) are one potential solution that use intrinsic variations of the device manufacturing process for provisioning security. In this work, we propose a novel weak PUF design using thermistor temperature sensors. Our design uses the differences in resistance variation between thermistors in response to temperature change. To generate a PUF that is reliable across a range of temperatures, we use a response-generation algorithm that helps mitigate the effects of temperature variation on the thermistors. We tested the performance of our proposed design across a range of environmental operating conditions. From this we were able to evaluate the reliability of the proposed PUF with respect to variations in temperature and humidity. We also evaluated the PUF’s uniqueness using Monte Carlo simulations.

A 124 fJ/Bit Cascode Current Mirror Array Based PUF With 1.50% Native Unstable Bit Ratio

In this paper, we present a novel physical unclonable function (PUF) design based on cascode current mirror array. By using a single-stage cascode amplifier for each PUF cell, the output impedance can be significantly elevated. Compared with a traditional single-stage amplifier-based current-mode PUF, the proposed structure is capable of generating more polarized voltage value for the output node. With an additional digital buffer, the temporal noise can be well-suppressed, and a rail-to-rail digital output can be provided with high native reliability. Moreover, through operating the transistors at the subthreshold region, the overall power consumption can be dramatically reduced. Featuring a compact footprint of $3.23~\mu \text{m}^{2}$ (i.e. 764 ${F}^{2}$ ) for each PUF cell, the proposed PUF implementation is validated using 65-nm standard CMOS process. The excellent randomness of the proposed PUF design is verified based on the test results with widely-accepted auto-correlation function and NIST suites. Meanwhile, the PUF’s uniqueness is measured with 10 chip prototypes and reported to be 49.94%. In addition, the fabricated PUF chips were also characterized with various environmental influences. With multiple readout (500 times) under the reference operating temperature of 27 °C and supply voltage of 1.2 V, the native unstable bit ratio is measured to be as low as 1.50%, which can be further improved to 0.79% by adopting the mainstream temporal majority voting (TMV)-based error correction scheme. Besides, we also evaluate the fabricated PUF chips’ reliability under varied operating temperature from −40 °C to 120 °C and supply voltage from 0.95 to 1.3 V. The averaged bit error rate (BER) per 10 °C and BER per 0.1 V are measured to be 0.86% and 1.02%, respectively. Compared with the state-of-the-art implementations, the reliability figure of merit (RFoM) is improved by $1.16\sim 4.29\times $ , with the influences of the temporal noise, the temperature/supply voltage variations and their ranges comprehensively considered.

The Interpose PUF: Secure PUF Design against State-of-the-art Machine Learning Attacks

The design of a silicon Strong Physical Unclonable Function (PUF) that is lightweight and stable, and which possesses a rigorous security argument, has been a fundamental problem in PUF research since its very beginnings in 2002. Various effective PUF modeling attacks, for example at CCS 2010 and CHES 2015, have shown that currently, no existing silicon PUF design can meet these requirements. In this paper, we introduce the novel Interpose PUF (iPUF) design, and rigorously prove its security against all known machine learning (ML) attacks, including any currently known reliability-based strategies that exploit the stability of single CRPs (we are the first to provide a detailed analysis of when the reliability based CMA-ES attack is successful and when it is not applicable). Furthermore, we provide simulations and confirm these in experiments with FPGA implementations of the iPUF, demonstrating its practicality. Our new iPUF architecture so solves the currently open problem of constructing practical, silicon Strong PUFs that are secure against state-of-the-art ML attacks.

Design of Robust, High-Entropy Strong PUFs via Weightless Neural Network

Physically unclonable functions (PUFs) have been explored as lightweight hardware primitives for the purpose of realizing robust security via strong authentication or secure key/ID generation. PUF harness manufacturing process variations for the purpose of generating binary keys or binary functions. An ideal strong PUF is a binary function that maps an m-bit input challenge to an uniquen-bit output response, making it attractive for authentication applications. Unfortunately, real strong PUF implementations suffer from reliability issues where the same challenge may produce different responses in the presence of noise. To overcome this problem, strong PUF leverages the availability of exponential number of challenge-response pairs (CRPs). A successful authentication event requires acquiring multiple CRPs and applying a threshold. In contrast, weak PUFs produce limited keys and are required to be highly reliable. Multiple techniques have been developed to achieve the necessary reliability. An additional prerequisite for strong PUFs is resilience against model-building attacks (cloning) by an adversary, who has observed a few CRPs, to prevent successful prediction of future CRPs. In this work, we first illustrate a strong PUF design that re-purposes a weightless neural network (WNN). Second, we showcase the robustness of WNN-based strong PUFs with respect to machine learning attacks, while providing desirable uniqueness and reliability metrics. Finally, we employ an initial entropy source of highly reliable weak PUF bits mapped to weightless neural networks (WNNs) for the purpose of creating a near-ideal strong PUF in terms of reliability. Our results show that it is possible to create highly reliable WNN–based strong PUFs with < 65 % ML accuracy by using as few as 32 initial reliable weak PUF bits.

XOR-Based Low-Cost Reconfigurable PUFs for IoT Security

With the rapid development of the Internet of Things (IoT), security has attracted considerable interest. Conventional security solutions that have been proposed for the Internet based on classical cryptography cannot be applied to IoT nodes as they are typically resource-constrained. A physical unclonable function (PUF) is a hardware-based security primitive and can be used to generate a key online or uniquely identify an integrated circuit (IC) by extracting its internal random differences using so-called challenge-response pairs (CRPs). It is regarded as a promising low-cost solution for IoT security. A logic reconfigurable PUF (RPUF) is highly efficient in terms of hardware cost. This article first presents a new classification for RPUFs, namely circuit-based RPUF (C-RPUF) and algorithm-based RPUF (A-RPUF); two Exclusive OR (XOR)-based RPUF circuits (an XOR-based reconfigurable bistable ring PUF (XRBR PUF) and an XOR-based reconfigurable ring oscillator PUF (XRRO PUF)) are proposed. Both the XRBR and XRRO PUFs are implemented on Xilinx Spartan-6 field-programmable gate arrays (FPGAs). The implementation results are compared with previous PUF designs and show good uniqueness and reliability. Compared to conventional PUF designs, the most significant advantage of the proposed designs is that they are highly efficient in terms of hardware cost. Moreover, the XRRO PUF is the most efficient design when compared with previous RPUFs. Also, both the proposed XRRO and XRBR PUFs require only 12.5% of the hardware resources of previous bitstable ring PUFs and reconfigurable RO PUFs, respectively, to generate a 1-bit response. This confirms that the proposed XRBR and XRRO PUFs are very efficient designs with good uniqueness and reliability.

Design of a Piezoelectric-Based Physically Unclonable Function for IoT Security

According to a report from McAfee and the center for strategic and international studies, worldwide financial loss due to cybercrime was estimated to be $600 billion in 2017. Researchers are currently exploring new methods for preventing cybercrime in Internet of Things (IoT) devices. Physically unclonable functions (PUFs) show promise as a device that could help in the fight against cybercrime. PUFs are a class of circuit that are unique and unclonable due to inherent variations caused by the device manufacturing process. We can take advantage of these PUF properties by using the outputs of PUFs to generate secret keys or pseudonyms that are similarly unique and unclonable. In recent years, energy harvesting devices, such as piezoelectric devices have been integrated with IoT devices for various purposes such as power generation and sensing applications. In this paper we propose a PUF design based on piezo sensors which are already commonly found in IoT devices. Our proposed PUF is tested in terms of reliability and uniformity.

A Chaotic Entropy Source based PUF Design for Secure IoT Platform

A chaotic entropy source based physical unclonable function (PUF) is proposed for the secure and low-power IOT platform. PUF is used to generate an encrypt key for data integrity of each transaction on IOT chain and device ID authentication to secure identification. The PUF use the true-random entropy source based on chaotic characteristics. Entropy core occupies 0.0045 ㎟ in 0.18 μm CMOS technology and consumes 65 nW at 270 kbps throughput with 0.6 V supply. The proposed Entropy Source passes all NIST tests.

A Theoretical Model to Link Uniqueness and Min-Entropy for PUF Evaluations

Physical unclonable functions (PUFs) are security primitives that enable the extraction of digital identifiers from electronic devices, based on the inherent silicon process variations between devices which occur during the manufacturing process. Due to the intrinsic and lightweight nature of a PUF, they have been proposed to provide security at a low cost for many applications, in particular for the internet of things (IoT). Many metrics have been proposed to evaluate the security and performance of PUF architectures, two of which are uniqueness and min-entropy. The uniqueness of a PUF response evaluates its ability to differentiate between different physical devices, while the min-entropy estimation is a measure of how much uncertainty the PUF response contains. The min-entropy is a lower-bound of real entropy. When the uniqueness of a PUF design is close to the optimal, it is unclear if this also implies that the design has a significantly high entropy; hence it would be useful to ascertain the minimum uniqueness required to achieve a given entropy. To date, a thorough investigation of the relationship between uniqueness and entropy for PUF designs has not been conducted. In this paper, this relationship between the uniqueness and entropy is explored, and for the first time, to the authors’ knowledge, the relationship between them is modeled. To verify this model, both simulated and hardware-based experimental results are performed, with a test-bed containing 184 Xilinx Artix-7 FPGA based Basys3 boards providing a large data set for granular results. The experimental results demonstrate that the proposed model accurately estimates the relationship between uniqueness and min-entropy, with both the theoretical analysis and software simulations closely matching the experimental results.

Efficient PUF-Based Key Generation in FPGAs Using Per-Device Configuration

Reconfigurable systems often require secret keys to encrypt and decrypt data. Applications requiring high security commonly generate keys based on physical unclonable functions (PUFs), circuits that use random manufacturing variations to produce secret keys that are unique to each device. Implementing PUFs on field-programmable gate arrays (FPGAs) is usually difficult, because the designer has limited control over layout, and each PUF system requires a large area overhead to correct errors in the PUF response bits. In this paper, we extend the state of the art for FPGA-based weak PUFs using a novel methodology of per-device configuration and a new PUF variant derived from the popular FPGA-specific Anderson PUF. The PUF is evaluated using Xilinx XC7Z020 programmable systemon-chips from the Virtex-7 family on Zynq ZedBoard platforms. The design we propose has several advantages over existing work including the Anderson PUF on which it is based. Our design is tunable to minimize the response bias and can be implemented using the common SLICEL components on Xilinx FPGAs. Moreover, the proposed PUF design enables an efficient per-device configuration that reduces bit error rate by over 10× at room temperature and improves response stability by over 2× across all temperatures. We demonstrate that the proposed per-device PUF configuration step leads to roughly 2× savings in area resources for PUFs and error correction as used in key generation.

An Energy-Efficient Current-Starved Inverter Based Strong Physical Unclonable Function With Enhanced Temperature Stability

As burgeoning hardware security primitive, physical unclonable function (PUF) has aroused the interest of solid-state circuit community on its efficient integration into security-critical applications. This paper presents an energy efficient implementation of classic arbiter PUF design. Current-starved (CS) inverters are inserted at the inputs of each multiplexer cell to reduce the skew and widen the distribution of the delay difference between two symmetric daisy-chained delay paths selectable by the input challenge. The CS-inverters are biased at the zero temperature coefficient (ZTC) point, making the accumulated delays of the two identical paths insensitive to temperature variations. A symmetric two RS latches based arbiter is proposed to overcome the asymmetric input and clock to the output propagation delay of D flip-flop and the metastability problem of RS latch arbiter. By limiting the drain currents of CS-inverters to achieve ZTC, the power consumption of the proposed PUF is also reduced substantially. The performance of the proposed PUF design has been successfully validated by the responses measured from prototype chips fabricated in standard 65 nm CMOS process. The fabricated chips feature a compact silicon area of 3838 μm 2 and low energy consumption of 2.74 pJ per bit at 25 Mbps, with measured uniqueness of 46.8% and native bit error rate (BER) of 0.8%. It is worst-case BER is less than 10.46% measured over an extended ~7× temperature range and ~5× supply voltage range. These physically measured figures of merit have outperformed previously reported measurements of strong PUFs with similar linear additive delay architecture.

A Lightweight LFSR-Based Strong Physical Unclonable Function Design on FPGA

Physical unclonable function (PUF), a reliable physical security primitive, can be implemented in FPGAs and ASICs. Strong PUF is an important PUF classification that provides a large “Challenge-Response” pairs (CRP) space for device authentication. However, most of the traditional strong PUF designs represented by the arbiter PUF are difficult to implement on FPGA. We propose a new lightweight strong PUF design that can dynamically reconfigure while maintaining high entropy and large CRP space. We implement the PUF on a 28-nm FPGA. The experimental results show that the uniformity of the PUF is 49.8%, the uniqueness is 49.9%, which is close to the ideal value, and the hardware overhead is very small. This design is easy to implement and suitable for device authentication on FPGA.

Inkjet-Printed EGFET-Based Physical Unclonable Function—Design, Evaluation, and Fabrication

Printed electronics (PE) is a promising technology that provides mechanical flexibility and low-cost fabrication and the key enabler for emerging applications, such as smart sensors, wearables, and Internet of Things. To use printed batteries or printed energy harvesters in the future, electrolyte-gated field-effect transistors (EGFETs) based on inorganic materials enable printed circuits requiring small supply voltage and low power. Since these applications need secure communication and/or authentication, it is imperative to embed security primitives for cryptographic key and identification purposes into the applications. Physical unclonable functions (PUFs) have been adopted widely to provide secure keys. In this paper, we present the design, simulation, fabrication, and measurements of a PUF based on EGFETs using inorganic inkjet PE. A comprehensive framework, including Monte Carlo simulations calibrated on real device measurements, is developed. Moreover, a multibit PE-PUF design is proposed to optimize area usage. Our simulation results show that the PE-PUF has ideal uniqueness (50.1%) and good reliability (89%). In addition, the proposed multibit PE-PUF reduces the area usage around 30%. The proposed PE-PUF was fabricated and the experimental results confirm that the PE-PUF can operate reliably as low as 0.5 V, and hence, it is a remarkable candidate to be utilized in low-power applications.

Low Pass Filter PUF: Authentication of Printed Circuit Boards Based on Resistor and Capacitor Variations

Physical Unclonable Functions (PUFs) are probabilistic circuit primitives that extract randomness from the physical characteristics of a device. PUFs are easy and simple to implement and its random nature makes its behavior hard to predict and model. Most existing PUF designs are based on variation at the chip level and can not be implemented in a printed circuit board (PCB). Therefore, these PUFs can not be used to protect against counterfeit PCBs in a distributed supply chain. In this work, we propose a novel PUF design based on resistor and capacitor variations for low pass filters (LoPUF). We demonstrate the setup in a protoboard for different resistor-capacitor pairs (RC pairs) for reliable low pass filter PUF. Because of process variations, the voltage will be different at the same cut-off frequency for our proposed PUF. Finally, the output of the filter is connected to an inverter to measure the pulse width and best suitable pulses are used for ID generation based on our algorithm.

Lorenz Chaotic System-Based Carbon Nanotube Physical Unclonable Functions

Physical unclonable function (PUF) is an advanced hardware security technology. Most conventional encryption approaches rely on the secure keys stored in nonvolatile memory, which are vulnerable to physical attacks. In contrast, PUF exploits the hardware fabrication variations to generate secure keys. As there are significant fabrication induced variations in carbon nanotube (CNT)-based circuits, they are natural candidates for building highly secure PUFs. However, existing PUFs are reported to be vulnerable to machine learning modeling attacks. In this paper, we develop a novel CNT PUF design through leveraging Lorenz chaotic system. Lorenz chaotic system magnifies the differences among responses of similar challenges. This salient feature gives the superior security performance, making the PUF design resistant to machine learning modeling attacks. Our experimental results demonstrate that these attacking methods can achieve very high bit-wise prediction rates for the standard CNT PUF. In contrast, when hacking the proposed Lorenz chaotic system-based CNT PUF, they become much less effective, where only up to 55% bit-wise prediction rates can be achieved.

CRPUF: A modeling-resistant delay PUF based on cylindrical reconvergence

Physical Unclonable Functions (PUFs) are devices which exploit manufacturing variability to uniquely distinguish individuals, thus preventing cloning for malicious purposes. With the increasing demand for low-cost devices, PUF designs which can effectively combine small silicon area and power consumption with high resistance to attacks have become of great interest. Unfortunately, many delay-based PUFs have revealed security weaknesses, making them less useful in such domains. This paper presents a novel delay-based strong PUF, the CRPUF (Cylindrical Reconvergence PUF). CRPUF is based on a carefully designed cylindrical XOR fabric, which allows for a large number of delay paths, thus producing a large combination of challenge-response pairs (CRPs) with relatively low transistor count. Simulations based on circuit delay variability models were performed to evaluate CRPUF with respect to well-known delay PUFs. The simulation results were then validated against an FPGA prototype to show that the desirable properties of the CRPUF can be obtained in a realistic physical implementation. Experiments show that CRPUF has Hamming Distance, Hamming Weight and Entropy comparable to the best results published so far, with acceptable levels of Bit Error Rate. Moreover, experiments also show that CRPUF is much more resistant to modeling attacks than other delay and some memory-based PUFs, making it a good candidate to systems which have stringent cost and security constraints.