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Abstract
As burgeoning hardware security primitive, physical unclonable function (PUF) has aroused the interest of solid-state circuit community on its efficient integration into security-critical applications. This paper presents an energy efficient implementation of classic arbiter PUF design. Current-starved (CS) inverters are inserted at the inputs of each multiplexer cell to reduce the skew and widen the distribution of the delay difference between two symmetric daisy-chained delay paths selectable by the input challenge. The CS-inverters are biased at the zero temperature coefficient (ZTC) point, making the accumulated delays of the two identical paths insensitive to temperature variations. A symmetric two RS latches based arbiter is proposed to overcome the asymmetric input and clock to the output propagation delay of D flip-flop and the metastability problem of RS latch arbiter. By limiting the drain currents of CS-inverters to achieve ZTC, the power consumption of the proposed PUF is also reduced substantially. The performance of the proposed PUF design has been successfully validated by the responses measured from prototype chips fabricated in standard 65 nm CMOS process. The fabricated chips feature a compact silicon area of 3838 μm 2 and low energy consumption of 2.74 pJ per bit at 25 Mbps, with measured uniqueness of 46.8% and native bit error rate (BER) of 0.8%. It is worst-case BER is less than 10.46% measured over an extended ~7× temperature range and ~5× supply voltage range. These physically measured figures of merit have outperformed previously reported measurements of strong PUFs with similar linear additive delay architecture.
Highlights
As forecasted by Gartner [1], 20.4 billion of Internet of Things (IoT) devices will be connected worldwide in 2020
One central feature of such disorder-based security is that each challenge response pair (CRP) of a Physical unclonable function (PUF) can be measured in real time, but the re-fabrication of another PUF with the same set of CRPs is infeasible or prohibitively costly even with the knowledge of the entire circuit down to the atomic level due to the very large entropy of physical disorder
Machine learning attacks can be thwarted effectively at protocol level as exemplified by techniques such as slender PUF [20], noise bifurcation [21], reconfigurable latent obfuscation [22], [23] and lockdown [24]. The latter approaches [23], [24] turn the disadvantage of machine learnable arbiter PUF into an advantage for lightweight model-based authentication by making the strong PUF easy to learn during enrollment but infeasible upon deployment and/or restricting the number of authentication events to limit the number of CRPs from being learned by the attackers
Summary
As forecasted by Gartner [1], 20.4 billion of Internet of Things (IoT) devices will be connected worldwide in 2020. Machine learning attacks can be thwarted effectively at protocol level as exemplified by techniques such as slender PUF [20], noise bifurcation [21], reconfigurable latent obfuscation [22], [23] and lockdown [24] The latter approaches [23], [24] turn the disadvantage of machine learnable arbiter PUF into an advantage for lightweight model-based authentication by making the strong PUF easy to learn during enrollment but infeasible upon deployment and/or restricting the number of authentication events to limit the number of CRPs from being learned by the attackers. The proposed PUF is taped out in a 65 nm CMOS process and their responses are measured to validate the performance improvements against existing physical implementation of strong PUFs based on similar linear additive delay architecture.
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