Abstract
The design of a silicon Strong Physical Unclonable Function (PUF) that is lightweight and stable, and which possesses a rigorous security argument, has been a fundamental problem in PUF research since its very beginnings in 2002. Various effective PUF modeling attacks, for example at CCS 2010 and CHES 2015, have shown that currently, no existing silicon PUF design can meet these requirements. In this paper, we introduce the novel Interpose PUF (iPUF) design, and rigorously prove its security against all known machine learning (ML) attacks, including any currently known reliability-based strategies that exploit the stability of single CRPs (we are the first to provide a detailed analysis of when the reliability based CMA-ES attack is successful and when it is not applicable). Furthermore, we provide simulations and confirm these in experiments with FPGA implementations of the iPUF, demonstrating its practicality. Our new iPUF architecture so solves the currently open problem of constructing practical, silicon Strong PUFs that are secure against state-of-the-art ML attacks.
Highlights
A Physical Unclonable Function (PUF) is a fingerprint of a chip which behaves as a one-way function in the following way: it leverages process manufacturing variation to generate a unique function taking “challenges” as input and generating “responses” as output
We do not test this attack on Interpose PUF (iPUF) designs with more Arbiter Physical Unclonable Function (APUF) components because our security against reliability-based machine learning attacks does not depend on the number of APUF components
We will discuss this situation in two cases: (a) Suppose that the delay values at the interposed stages of the lower y-XOR APUFs are very small comparing with the other delay values, the delay introduced by the interposed stages are very small, but the response of the upper x-XOR APUF still affects the final response of y-XOR APUF
Summary
A Physical Unclonable Function (PUF) is a fingerprint of a chip which behaves as a one-way function in the following way: it leverages process manufacturing variation to generate a unique function taking “challenges” as input and generating “responses” as output. The fundamental open problem of strong silicon PUFs is: How to design a PUF that is lightweight, strong and secure. A lightweight design must have a small number of gates (small area) and in addition only limited digital computation is allowed with only a small number of gate computations and without the need for accessing additional memory. This lightweight implementation gives a small hardware footprint and high throughput. The most efficient CML attack on APUF and XOR APUF [RSS+10, TB15] is Logistic Regression (LR) which uses non-repeated measurements of CRPs. LR was used to break APUFs and XOR APUFs in 2010 [RSS+10]. For larger x the XOR APUF has been shown to resist LR due to the subexponential relationship between x and the amount of training data required to model the XOR APUF [Söl, RSS+10, TB15]
Sign-in/Register to view highlights & summary Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callMore From: IACR Transactions on Cryptographic Hardware and Embedded Systems
Disclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
