Physical Unclonable Function Cell Research Articles

A BER-Suppressed PUF With an Amplification of Process Mismatch Effect in an Oscillator Collapse Topology

The physically unclonable function (PUF) has been implemented with circuits that perform amplification of randomly given small process mismatch by using an explicit amplifier or by making a signal path repeatedly experience the same delay skew in an oscillator. Though the amplifier approach provides a fast response, it is vulnerable to noise at the first stage of amplification. On the other hand, the oscillator-based scheme requires a longer time to develop a digital output while achieving good noise immunity. This article proposes a PUF circuit exploiting a hybrid architecture, which combines a process skew amplification scheme in an oscillator collapse topology. The proposed scheme compensates for the drawbacks of the two approaches while achieving merits of them, i.e., high sensitivity to process variation and good immunity to noise. The supply rails of an even-stage ring oscillator (RO) are alternately fed from a diode-based threshold-sampling block. An IC with an array of 128 PUF cells is fabricated in 40-nm CMOS, showing a native bit error rate (BER) of 0.027%. Processing of 7-b temporal majority voting (TMV7) with a 3.64% masking demonstrates an error-free operation in a nominal condition. It shows a BER of 0.0019% in the worst condition under a voltage range of 0.7–1.4 V and a temperature range of −40 °C to 125 °C.

A Fully Configurable PUF Using Dynamic Variations of Resistive Crossbar Arrays

A resistive random access memory (RRAM) as an emerging nanoelectronic device, is widely used for memory and physical unclonable function (PUF) applications. The compatibility of RRAM PUFs with memory architectures can be exploited to reduce the hardware overhead. Therefore, an intrinsic PUF using dynamic variations of resistive crossbar arrays is presented in this paper. Based on an improved sense amplifier (SA), the proposed intrinsic RRAM PUF can be fully configured as a memory cell or a PUF cell, leading to a minimal design overhead. Using the device-to-device (D2D) variation of an RRAM, a significant number of challenge-response pairs (CRPs) is generated with a flexible configuration of the resistive crossbar arrays. The proposed RRAM PUF can be refreshed to a new instance relying on the cycle-to-cycle (C2C) variation of an RRAM. An efficient challenge generation method is presented to improve the security of the proposed RRAM PUF. To verify the performance of the proposed RRAM PUF, 20 instances are simulated and implemented using a compact Spice model and a UMC 65 nm CMOS process technology, respectively. The simulation results show that the proposed RRAM PUF exhibits good performances with a high uniqueness, reliability, and reconfigurability. The randomness of the PUF is evaluated by the National Institute of Standards and Technology (NIST) and autocorrelation function (ACF) tests. Moreover, the experimental results show that the proposed RRAM PUF achieves a good resistance against machine learning (ML) attacks.

A Highly Reliable RRAM Physically Unclonable Function Utilizing Post-Process Randomness Source

Physically unclonable function (PUF) has been increasingly used as a promising primitive for hardware security with a wide range of applications in the Internet of Things (IoT). In recent years, novel PUF techniques based on resistive switching mechanism in various emerging nonvolatile memories have demonstrated superior performance on reliability and integration density. In this work, a resistive random access memory (RRAM)-based PUF chip with 8-kb capacity is developed. Two operation modes, namely differential mode and median mode, are embedded on chip. To implement these modes, a current sampling-based sense amplifier is designed to distinguish the current values of the PUF cells and the reference cell. In addition, a split-resistance scheme is proposed to enhance the PUF's reliability significantly. The experiment results show that the differential PUF exhibits excellent performance with native bit error rate (N-BER) below 6 × 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-6</sup> and inter-Hamming distance (inter-HD) of 49.99%. In the meanwhile, the reconfigurability of PUF challenge-response pairs (CRPs) is demonstrated with 49.77% and 47.29% reconfigure-Hamming distance (reconfigure-HD) in the median mode and the differential mode, respectively.

An All-MOSFET Voltage Reference-Based PUF Featuring Low BER Sensitivity to VT Variations and 163 fJ/Bit in 180-nm CMOS

In this article, a novel subthreshold voltage reference (VR)-based physical unclonable function (PUF) is presented. With two native nMOS transistors stacked on top for providing bias current and two bottom low threshold voltage (LVT) nMOS transistors forming the self-cascode MOSFETs structure, a 4T all-MOSFET VR is proposed, which features low power consumption and high stability under largely varied VT conditions for the wide range of Internet of Things (IoT) applications. By integrating a pair of the proposed VRs and a digital voltage comparator in each PUF cell, the mismatched output voltages of the VR pair can be locally compared and digitized immediately with the system's power on, leading to ultrashort signal path and maximized immunity to the influence of temporal noise. Fabricated using standard 0.18- μm CMOS process, the proposed PUF design is validated based on extensive measurement results of 20 PUF chips. By passing the widely exploited bias test, National Institute of Standards and Technology (NIST) test and autocorrelation function (ACF) test, the proposed PUF's excellent randomness is well-verified. In addition, the uniqueness is measured to be 49.92%, and the bit error rate (BER) sensitivities in terms of BER per 10 °C and BER per 0.1 V are averaged and reported to be 0.39% and 0.26%, for the temperature range of -40 °C-120 °C and supply voltage range of 1.2-1.8 V, respectively. Moreover, by operating the proposed implementation at a throughput of 50 Mb/s, the measured overall energy consumption is reported to be as low as 163 fJ/bit.

A 108 F2/Bit Fully Reconfigurable RRAM PUF Based on Truly Random Dynamic Entropy of Jitter Noise

In this paper, we present a fully reconfigurable resistive random access memory (RRAM) physical unclonable function (PUF) based on the truly random dynamic entropy of the ubiquitous jitter noise, which is intrinsically different from most previously demonstrated PUF implementations with semiconductor fabrication’s process variation as the static entropy source. In addition, the proposed RRAM PUF is operated by configuring the mainstream RRAM cells to either high resistance state (for ‘1’) or low resistance state (for ‘0’), according to the customized ring oscillator (RO) true random number generator’s digital output that is determined by the random jitter noise. By completely removing the need of dedicated split resistance circuitry (SRC) in existing RRAM PUFs, the proposed implementation is fully compatible with the SET/RESET operations of the RRAM array for mainstream memory applications, leading to minimized design overhead and enhanced reliability without SRC-caused error bits. Fabricated using 130 nm standard complementary-metal-oxide-semiconductor (CMOS) process plus post-processing dedicated to the RRAM devices, the proposed RRAM PUF cell features an ultra-compact footprint of $1.82~\mu \text{m}^{2}$ (i.e., 108 $F^{2}$ ), which is capable of generating ~107 PUF bits per cell due to the time-variant property of jitter noise and the full reconfigurability of the RRAM PUF. This significantly innovates all the previous weak PUF implementations based on the static entropy source of process variation, where the maximum bit number per PUF cell is always limited and fixed after the chip fabrication. Meanwhile, ultra-low native unstable bits of 0.28% and bit error rate (BER) per 10°C of 0.03% can be achieved for the fabricated RRAM PUF. Moreover, by passing the widely-adopted bias test, National Institute of Standards and Technology (NIST) test and autocorrelation function (ACF) test under various VT conditions, the true randomness of the customized RO TRNG’ dynamic entropy is validated using 65 nm standard CMOS process. Compared with the state-of-the-art weak PUF implementations, the native unstable bits is improved by $5.36\times $ and the BER per 10°C is improved by $4\times $ , even under the widest operating temperature range from −50°C to 150°C.

An Ultracompact Switching-Voltage-Based Fully Reconfigurable RRAM PUF With Low Native Instability

In this brief, an ultracompact and highly reliable physical unclonable function (PUF) is presented based on the mainstream resistive random access memory (RRAM) devices. With the entropy originating from the switching voltage between the high-resistance state (HRS) and the low-resistance state (LRS), the proposed RRAM PUF can be generated during the RRAM's standard SET operation, leading to minimized design overhead. In addition, different from the previous implementations where the adopted RRAM PUF cells are dedicated to the “PUF” function, the proposed RRAM PUF is fully reconfigurable between the “PUF” function and the normal memory function. Moreover, the proposed implementation is validated using a standard 0.13-μm CMOS process plus customized postprocessing dedicated to RRAM devices. Featuring a normalized PUF cell area of 108F <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , the native instability (i.e., unstable bits) is measured to be as low as 0.28% at the normal condition. With the operating temperature varying from -50 °C to 150 °C and the supply voltage varying from 4 to 6 V, the averaged bit error rate (BER) is reported to be as low as 0.06% and 0.095%, respectively.

A Unified Memory and Hardware Security Module Based on the Adjustable Switching Window of Resistive Memory

Physically unclonable function (PUF) and true random number generator (TRNG) are critical primitives to provide lightweight hardware protection. As area is tightly restricted in IoT applications, merging PUF and TRNG is a novel trend to achieve higher area efficiency. In this work, a novel tri-functional module is proposed and experimental demonstrated using RRAM for the first time. A two-phase forming process is designed to generate and store PUF ID utilizing the impact of different forming conditions on the switching window. As PUF ID is stored by the switching window, instead of a fixed resistance, PUF cells can be written to low resistance state and high resistance state as usual, and can be used as memory and TRNG. The inter-Hamming distance of the generated PUF IDs approaches 0.5, and with the majority voting readout strategy, low BER can be achieved in a wide range of temperatures from −40°C to 125°C. TRNG produces the true random numbers based on the parity of the number of pulses consumed in a write-zero process. The generated random numbers are uniform and uncorrelated after XORed, and the statistical randomness is verified by NIST SP800-22 tests.

A 2 Bit/Cell Tilting SRAM-Based PUF With a BER of 3.1E-10 and an Energy of 21 FJ/Bit in 65nm

An SRAM-based Physical Unclonable Function (PUF) with two independent bits/cells is presented along with a tilting preselection test designed to identify all the unstable bits. Results of analysis of the Decision Voltage of the SRAM-based PUF cell indicate that in certain conditions, only the NMOS transistors in the cell impact its response, whereas the PMOS devices are in cutoff. Two pairs of NMOS transistors are inserted in the cell, each of which represents an orthogonal bit. The tilt test evaluates the internal mismatch within each of the NMOS pairs so that if it is insufficient, the resulting bit is considered unstable and masked from the PUF response. The cell demonstrated a highly competitive area of 1420F <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> per bit, a bit-error-rate (BER) of 3.1E-10, and a very low energy consumption of 21fJ/bit in 65nm. After preselection, the 2 bit/cell PUF exhibited a near-ideal inter-chip Hamming distance (49.5%) and percentage of ones (50.6%).

A Physically Unclonable Function Using Soft Oxide Breakdown Featuring 0% Native BER and 51.8 fJ/bit in 40-nm CMOS

This paper presents a physically unclonable function (PUF) based on the randomness of soft gate oxide breakdown (BD) locations in MOSFETs, namely, soft-BD PUF. The proposed PUF circuit features a self-limiting mechanism that generates exactly one soft-BD spot in a pair of NMOS transistors. Highly stable “0” and “1” bits with an equal probability of 0.5 are extracted based on the locations of the generated BDs. A differential readout scheme is employed based on the proposed reference-free sense amplifier (SA), resulting in good current sensitivity and side-channel attack resilience. The soft-BD PUF, fabricated in a 40-nm CMOS process, comprises all essential periphery circuits. Measurements show that the soft-BD PUF has good data stability in a wide operating range. The native bit error rate is 0% for V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DD</sub> = 1 V and above, shown by measuring 10k readout cycles among 10k PUF cells. Data stability degrades at lower supply voltage and higher temperature due to the conductivity of PUF cells and the offset of SAs. Under the nominal V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DD</sub> of 0.9 V in this technology, the throughput is shown to be at least 40 Mb/s and the PUF readout consumes only 51.8 fJ/bit. The averaged hamming weight and hamming distance are 0.497 and 0.496, respectively, showing a good randomness and uniqueness. The resulting PUF data show good statistical properties by passing all the relevant tests in the NIST 800-22 suite.

A 124 fJ/Bit Cascode Current Mirror Array Based PUF With 1.50% Native Unstable Bit Ratio

In this paper, we present a novel physical unclonable function (PUF) design based on cascode current mirror array. By using a single-stage cascode amplifier for each PUF cell, the output impedance can be significantly elevated. Compared with a traditional single-stage amplifier-based current-mode PUF, the proposed structure is capable of generating more polarized voltage value for the output node. With an additional digital buffer, the temporal noise can be well-suppressed, and a rail-to-rail digital output can be provided with high native reliability. Moreover, through operating the transistors at the subthreshold region, the overall power consumption can be dramatically reduced. Featuring a compact footprint of $3.23~\mu \text{m}^{2}$ (i.e. 764 ${F}^{2}$ ) for each PUF cell, the proposed PUF implementation is validated using 65-nm standard CMOS process. The excellent randomness of the proposed PUF design is verified based on the test results with widely-accepted auto-correlation function and NIST suites. Meanwhile, the PUF’s uniqueness is measured with 10 chip prototypes and reported to be 49.94%. In addition, the fabricated PUF chips were also characterized with various environmental influences. With multiple readout (500 times) under the reference operating temperature of 27 °C and supply voltage of 1.2 V, the native unstable bit ratio is measured to be as low as 1.50%, which can be further improved to 0.79% by adopting the mainstream temporal majority voting (TMV)-based error correction scheme. Besides, we also evaluate the fabricated PUF chips’ reliability under varied operating temperature from −40 °C to 120 °C and supply voltage from 0.95 to 1.3 V. The averaged bit error rate (BER) per 10 °C and BER per 0.1 V are measured to be 0.86% and 1.02%, respectively. Compared with the state-of-the-art implementations, the reliability figure of merit (RFoM) is improved by $1.16\sim 4.29\times $ , with the influences of the temporal noise, the temperature/supply voltage variations and their ranges comprehensively considered.

A 4-fJ/b Delay-Hardened Physically Unclonable Function Circuit With Selective Bit Destabilization in 14-nm Trigate CMOS

This paper describes a full-entropy 128-b key generation platform based on a 1024-b hybrid physically unclonable function (PUF) array, fabricated in 14-nm trigate high-k/metal-gate CMOS. Delay-hardened hybrid PUF cells use differential clock delay insertion to favor circuit evaluation in the desired direction while leveraging burn-in-induced aging for selective bit destabilization enabling quick identification and masking of unstable cells, and subsequent temporal-majority-voting with soft dark-bit masking to reduce PUF bit error by 3.9 times to 1.45% resulting in ~5 ppb failure probability. A stable full-entropy 128-b key is finally generated from the 1024 raw PUF bits using BCH error correction and AES-CBC-based entropy extraction. An all-digital design with compact PUF cell layout occupying $1.84~\mu \text{m}^{2}$ achieves: 1) 4-fJ/b energy-efficiency with 3-μW leakage at 0.65 V, 70 °C; 2) peak operating frequency of 1 GHz resulting in 1.2-μs key generation latency; 3) robust operation with stable key generation across 0.55–0.75 V, and 25 °C–110 °C; 4) 14 times separation between intra/inter-PUF hamming distances with 0.99993 entropy ensuring cryptographic quality randomness and uniqueness; 5) 48% higher PUF stability with long-term aging by leveraging transistor degradation to reinforce favorable cell bias; and 6) resiliency to power cycling attacks with common centroid clock routing measured from 49.5% hamming distance between array’s evaluation and wake-up states.

MRAM PUF: A Novel Geometry Based Magnetic PUF With Integrated CMOS

This manuscript addresses a novel MRAM-based physically unclonable function (PUF). The PUF responses are generated using the unique energy-tilt, which is an outcome of the random geometric variations in the MRAM cells. We have verified relevant attributes of this PUF through extensive magnetic simulations and in-house fabrication results. Our fabricated PUF cells generate entropy as high as 0.99, which is comparable to most of its competitors. To our knowledge, the footprint of the PUF cells is also lower than the majority of silicon PUFs. Also, the authentication control algorithm for this PUF requires very low additional control-steps. We conclude our discussion of this novel PUF with a study of authentication overhead and protocols required by the PUF system in terms of area, power, and delay.

Design of lightweight PUF circuit based on selectable cross-coupled inverters

By analyzing the principle of process variations, a lightweight Physical Unclonable Function (PUF) circuit based on selectable cross-coupled inverters is proposed in this paper. Firstly, selectable cross-coupled inverters are chosen for two delay paths. Simultaneously, the circuit takes challenge signal to control each delay path. The PUF cell circuit is implemented in Semiconductor Manufacturing International Corporation (SMIC) 65 nm CMOS technology and the layout area is 2.94 μm × 1.68 μm. Then the 64-bit PUF circuit is achieved with the cascade connection of cell circuits. The simulation results show that the randomness is 49.4% and the reliability is 96.5%. Compared to the other works, this PUF circuit improves the encrypt performance and greatly reduces the area.