Strenuous efforts are being focused on further scaling of metal-oxide-semiconductor field-effect transistors (MOSFETs) into the sub-100 nm regime. Complementary MOS devices (CMOS) fabricated on silicon-oninsulator (SOI) wafers have attracted a lot of attention because of the advantages of full dielectric isolation and reduced junction capacitance over those on bulk silicon wafers in regard to integrated circuit (IC) applications for low stand-by power and high performance. Moreover, the fabrication technique involved in SOI MOSFET can remove or relax some of the process and material constraints on the MOSFET scaling, because it provides a low leakage current, latch-up elimination, high soft error immunity, smaller subthreshold swing, and a simple device structure and process. However, one of the major challenges to overcome is the ultra-shallow junction formation method, which prevents short channel effects for deep sub-100 nm devices [1, 2]. The conventional approach for junction formation is ion implantation with low-energy ion beams. The crystal defects associated with the energetic ion beam bombardment are unavoidable and act as the primary source of junction leakage currents. The junction leakage degrades the device performance and leads to an increase in power consumption. Therefore, an alternative method is required to make use of the advantages of the SOI devices. Doping using solid-phase diffusion (SPD) is an effective method to form damage-free ultra-shallow junctions. In this paper, we report the doping properties of the SPD method and the electrical characteristics of sub-100 nm SOI MOSFETs fabricated using the SPD technique for ultra-shallow source and drain junction formation. The phosphorus doped oxide films used as the SPD source are usually prepared by chemical vapor deposition (CVD), but we used a liquid-state dopant source containing silicon, oxygen and phosphorus. A wafer was coated with the dopant source using a spin coating technique. After baking at 250 ◦C for 20 min, the liquid source was converted to a solid phosphorus doped silicon oxide layer on the top of the wafer. The refractive index and density of this oxide layer were 1.42 and 2.05 g/cm3, respectively. Then the coated wafer was placed in a rapid thermal annealing (RTA) system and a PN junction was created after the phosphorus had diffused into the silicon. In this way, N+P junction diodes and SOI MOSFETs were fabricated. Fig. 1 shows the secondary ion mass spectrometry (SIMS) depth profile of phosphorus for various RTA process temperatures. The RTA process was performed for 30 s in N2 ambient. The diffusion depth of the phosphorus increases with RTA temperature. The surface concentration of phosphorus also increased with the RTA temperature due to the enhanced solid solubility of phosphorus atoms. In nano-scale MOSFET devices, a channel impurity concentration of 1018 cm−3 is required to suppress the short channel effect. It is clear that a shallow junction, less than the 50 nm deep, defined at 1 × 1018 cm−3 can be obtained when the RTA temperature is below 925 ◦C. Fig. 2 shows the relationship between the sheet resistance (Rs) measured using the four-point probe and RTA temperature. The Rs monotonically decreases as the RTA temperature and junction depth increase. The Rs is lower than 1 k Ohm/cm2 at 925 ◦C, which is the maximum drain extension sheet resistance required for 32 nm-technology [3]. Since the surface dopant concentration increased as the RTA temperature increased, more improvements can be expected with control of RTA duration time. Fig. 3 shows the current-voltage (I-V) characteristics of N+P diodes fabricated on SOI substrates by SPD methods. In order to verify the effectiveness of the SPD process, the I-V characteristics of N+P diodes fabricated by the plasma doping method, which is often used in ultra-shallow junction formation, are also shown in Fig. 3 for comparison. It is observed that the forward bias current depends on the RTA temperature. As the RTA temperature increased, the forward bias current increased, while the reverse bias current remained almost constant. The increase in forward bias current could be attributed to the reduction of sheet resistance resulting from high temperature RTA. In the case of the plasma doping sample, the forward bias cur-
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Jul 15, 2007
Zhen Yi Shao + 4
Open Access