Clock Phase Research Articles

Two-Time Procedure for Calculation of Carrier Frequency of Phasomodulated in Communication Systems

The use in radio communication systems of phase modulation of a signal intended for the transmission of useful information in a continuous mode creates the problem of frequency uncertainty of the received signal by frequency.In practice, it is not possible to implement frequency estimation in the conditions of chat uncertainty of the signal in the channel with low energy of the signal received in the continuous mode. Therefore, the estimation of the carrier frequency offset of the signal received relative to the nominal value is carried out before other synchronization procedures are included, namely: phase synchronization and clock synchronization. The paper generalizes the procedure and forms a two-step procedure for calculating the carrier frequency of the phase-modulated signal of a radio communication system for data transmission in a continuous mode, taking into account the condition of uncertainty of all signal parameters. Achieving the minimum observation interval in the given order of calculation of the carrier frequency is ensured by the use of the fast Fourier transform function. In order to analyze the effectiveness of this procedure, the process of estimating the carrier frequency of the phase-modulated signal of the radio communication system during data transmission in continuous mode and functional dependences of the maximum frequency in the signal spectrum and the minimum variance of carrier frequency estimation. This procedure allows a two-stage assessment of the carrier frequency according to the rule of maximum likelihood, taking into account the condition of uncertainty of all parameters of the signal received by the satellite communication system in a continuous mode with a minimum observation interval. Achieving the minimum observation interval in the given order of carrier frequency estimation is ensured by using the fast Fourier transform function and two estimation steps. The analysis of the efficiency of the estimation of the specified order was carried out on the basis of comparison of a ratio of the received minimum variance of an estimation of a carrier frequency and theoretically possible border of the minimum variance.

A New Nano-Design of a Fault-Tolerant Coplanar RAM with Set/Reset Ability Based on Quantum-Dots

Quantum Dot Cellular Automata (QCA) is a recent technology that has piqued researchers’ interest because of its small size and low energy consumption. With the help of quantum dots, the QCA technology delivers a new computational foundation for constructing digital circuits. Medical imaging and quantum computing are just a few applications for quantum dots. Quantum dots are nanocrystals that transmit data at the nano-scale. Since the memory is an important digital circuit, this work proposes a fault-tolerant loop-based coplanar Random Access Memory (RAM) with set/reset capability that uses the QCA rules. The memory cell’s operation is verified both physically and through simulations with the QCADesigner program. The quantum cost of the proposed memory cell shows that it has a negligible quantum cost. The proposed QCA-based memory circuit performs well in simulations, with 96 QCA cells and the output signal generated after 0.75 clock phases. The gates and wire in this design have around 85 percent better fault-tolerant capability than the best-presented memory systems. Furthermore, this circuit can tolerate most cell omission, displacement, misalignment, and deposition faults. This structure can be used to create high-performance higher-order fault-tolerant memory structures.

Clock Synchronized Transmission of 51.2 GBd Optical Packets for Optically Switched Data Center Interconnects

Optical switching has attracted significant attention in recent research on data center networks (DCNs) as it is a promising viable route for the further scaling of hyper scale data centers, so that DCNs can keep pace with the rapid growth of machine-to-machine traffic. It has been shown that optical clock synchronization enables sub-nanosecond clock and data recovery time and is crucial to high performance optically switched DCN. Moreover, the interconnect data rate is expected to increase from the current 100 Gb/s per fiber to scale to 800 Gb/s and beyond, requiring high baud rate signaling at >50 GBd. Thus, future optically switched DCN should support >50 GBd data transmission with optical clock synchronization. Here, we demonstrate the clock-synchronized transmission of 128-byte optical packets at 51.2 GBd and study the impact of reference clock phase noise on system performance, focusing on the tolerance to the clock phase misalignment that affects the system scalability and reliability. By comparing the tolerable sampling clock phase offsets using different reference clocks, we show that a clock phase offset window of about 8 ps could be achieved with a <0.2ps source clock. Furthermore, we model and numerically study the de-correlation of clock phase noise. This allows the total jitter to be estimated, and thereby, the estimation of the transmission performance for future generations of high baud rate, clock synchronized DC interconnects.

Modeling the Performance of the Clock Phase Caching Approach to Clock and Data Recovery

Optical switching could enable data center networks to keep pace with the rapid growth of intra-data center traffic, however, sub-nanosecond clock and data recovery time is crucial to enabling optically-switched data center networks to transport small packet dominated data center traffic with over 90% efficiency. We review the clock-synchronized approach to clock and data recovery, which enables sub-nanosecond switching time in optically switched networks. We then introduce an analytical model to mathematically explore the operation of clock phase caching, and use this model to explore the impact of factors such as fiber temperature, clock jitter and symbol rate on the BER and clock and data recovery locking time performance of the clock phase caching approach, as well as their impact on scalability. Using commercial data center parameters matching those used in our previous experimental research, we find that our analytical model provides estimates that closely match our previous experimental results, validating its use for making predictions of the performance of clock phase cached systems.

Isochronous data link across a superconducting Nb flex cable with 5 femtojoules per bit *

Interconnect properties position superconducting digital circuits to build large, high performance, power efficient digital systems. We report a board-to-board communication data link, which is a critical technological component that has not yet been addressed. Synchronous communication on chip and between chips mounted on a common board is enabled by the superconducting resonant clock/power network for Reciprocal Quantum Logic circuits. The data link is extended to board-to-board communication using isochronous communication, where there is a common frequency between boards but the relative phase is unknown. Our link uses over-sampling and configurable delay at the receiver to synchronize to the local clock phase. A single-bit isochronous data link has been demonstrated on-chip through a transmission line, and on a multi-chip module through a superconducting tape between driver and receiver with variable phase offset. Measured results demonstrated correct functionality with a clock margin of 3 dB at 3.6 GHz, and with 5 fJ bit−1 at 4.2 K.

A spatial model of the plant circadian clock reveals design principles for coordinated timing

Individual plant cells possess a genetic network, the circadian clock, that times internal processes to the day‐night cycle. Mathematical models of the clock are typically either “whole‐plant” that ignore tissue or cell type‐specific clock behavior, or “phase‐only” that do not include molecular components. To address the complex spatial coordination observed in experiments, here we implemented a clock network model on a template of a seedling. In our model, the sensitivity to light varies across the plant, and cells communicate their timing via local or long‐distance sharing of clock components, causing their rhythms to couple. We found that both varied light sensitivity and long‐distance coupling could generate period differences between organs, while local coupling was required to generate the spatial waves of clock gene expression observed experimentally. We then examined our model under noisy light‐dark cycles and found that local coupling minimized timing errors caused by the noise while allowing each plant region to maintain a different clock phase. Thus, local sensitivity to environmental inputs combined with local coupling enables flexible yet robust circadian timing.

A 2.4–8 GHz Phase Rotator Delay-Locked Loop Using Cascading Structure for Direct Input–Output Phase Detection

This paper presents a phase rotator (PR)-based delay-locked loop (DLL) for a dynamic random-access memory interface in 28-nm CMOS technology. A direct input-output comparison using a sub-sampling technique reduces the effect of a timing mismatch of a replica delay line for synchronizing an input clock and output strobe clock. A divided clock samples the input clock for phase alignment. A 4-b analog-to-digital converter was used for input phase acquisition. The output phase is aligned with respect to the sampling clock phase using a bang-bang phase detector. Two DLLs for the input-output synchronization are implemented in a cascade structure, and the loop delay of the replica delay line is considerably reduced. In the proposed DLL, a PR delay line using an 8-phase clock generator is adopted for linearity to reduce the phase difference of the phase interpolation from π/2 to π/4. The resolution of the PR-DLL is 7-b of 2π, which consists of a 3-b coarse and a 4-b fine control. The DLL operates from 2.4 to 8 GHz, and the power dissipation at the maximum input frequency is 20.2 mW. The measured clock root mean square jitter was 1.68 ps. According to the simulation results, the phase mismatch between the input and output clocks was reduced by 80.5%.

A 50-Gb/s PAM-4 Silicon-Photonic Transmitter Incorporating Lumped-Segment MZM, Distributed CMOS Driver, and Integrated CDR

This article presents a 50-Gb/s optical transmitter (TX), consisting of a 40-nm distributed CMOS driver and a 180-nm silicon-photonic modulator. A lumped-segment Mach–Zehnder modulator (LS-MZM) is developed for high bandwidth (BW) four-level pulse amplitude (PAM-4) modulation. A multi-segment driver with limiting outputs is co-designed, which is distributed into each LS-MZM segment. By grouping these LS-MSM segments in a thermometer code, high-linearity modulation is realized without the need of power-hungry high-swing linear drivers. To improve the optical PAM-4 signal integrity, in-segment multiplexing along with clock phase interpolation is adopted to synchronize the electrical and optical signals across all segments. The hybrid coupling between the driver and modulator is devised to boost the BW of the high-speed data path, while a half-rate clock and data recovery (CDR) circuit is integrated to remove the accumulated jitter. Measurements show that the TX exhibits an extinction ratio (ER) of up to 9.8 dB and a 0.99 ratio of the level mismatch. A figure-of-merit (FoM) of 1.39 pJ/bit/dB corresponds to a 682-mW power, which can be further reduced by 40%, at the cost of a degraded ER of 4 dB. The PAM-4 CDR helps to achieve <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$&lt; 10^{-12}$ </tex-math></inline-formula> BER and >0.1- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{U}I_{\mathrm {pp}}$ </tex-math></inline-formula> jitter tolerance (JTOL) from 10 to 100 MHz.

Diurnal shift of mouse activity by the deficiency of an ageing-related gene Lmna.

Nuclear lamina is a fundamental structure of the cell nucleus and regulates a wide range of molecular pathways. Defects of components of the nuclear lamina cause ageing-like physiological disorders, called laminopathy. Generally, ageing and diseases are often associated with perturbation of various time-of-day-dependent regulations, but it remains elusive whether laminopathy induces any changes of the circadian clock and physiological rhythms. Here, we demonstrated that deficiency of Lmna gene in mice caused an obvious shift of locomotor activities to the daytime. The abnormal activity profile was accompanied by a remarkable change in phase angle between the central clock in the suprachiasmatic nucleus (SCN) and the lung peripheral clocks, leaving the phase of the SCN clock unaffected by the mutation. These observations suggest that Lmna deficiency causes a change of the habitat from nocturnal to diurnal behaviours. On the other hand, molecular oscillation and its phase resetting mechanism were intact in both the Lmna-deficient cells and progeria-mimicking cells. Intriguingly, high-fat diet feeding extended the short lifespan and ameliorated the abnormalities of the behaviours and the phase of the peripheral clock in the Lmna-deficient mice. The present study supports the important contribution of the energy conditions to a shift between the diurnal and nocturnal activities.

A 6.15–10.9 Gb/s 0.58 pJ/Bit Reference-Less Half-Rate Clock and Data Recovery With “Phase Reset” Scheme

This paper presents a low power injection-locked oscillator (ILO)-type clock and data recovery (CDR) in 40 nm CMOS. An efficient ``phase reset'' scheme is proposed to periodically realign the clock phase to the rising edge of data. The frequency information is extracted by comparing the rising edge of the data and the clock after aligning the phase using a bang-bang phase detector (BBPD). Additionally, a low power injection-locked two-stage ring digitally controlled oscillator (ILDCO) is employed to provide four-phase quadrature clock and significantly reduce the power consumption. Based on the proposed architecture, the fabricated CDR consumes only 5.8 mW from a 0.9 V supply, while being able to extract the clock signal from 6.15 to 10.9 Gb/s input data with a measured jitter tolerance (JTOL) of 0.15 UIpp at the highest frequency, indicating that the CDR meets the OC-192 mask. Furthermore, the proposed CDR demonstrates a substantial improvement in the power efficiency of 0.58 pJ/bit.

A 48 GHz Fundamental Frequency PLL with Quadrature Clock Generation for 60 GHz Transceiver

This paper presents a design of a 48 GHz CMOS phase-locked loop (PLL) for 60 GHz millimeter-wave (mmWave) communication systems. For the sliding intermediate frequency (sliding-IF) transceiver applications, a fundamental frequency PLL with quadrature clock generation scheme is proposed. Specifically, with an implicit capacitive-bridged shunt peaking network, a second order harmonic filtering technique is realized in the voltage control oscillator (VCO) to broaden the bandpass response, thereby avoiding the complex common-mode resonant tank calibration and improving the phase noise performance. A robust current mode logic (CML) static frequency divider topology is adopted to realize the prescaler and to generate the quadrature clock. With the capacitive-bridged shunt peaking load and robust biasing circuit, the static frequency divider locking range and high frequency performance is improved and its reliability is enhanced over the PVT corners. To improve the image suppression ratio of the transceiver, a quadrature clock phase calibration scheme is proposed and verified. Fabricated in a 65 nm CMOS process, the PLL occupies a core area of 800 μm × 950 μm. Over the frequency range of 45.2 to 52.6 GHz, the measured PLL in-band phase noise PLL is better than −90 dBc/Hz@100 KHz offset, and its jitter is less than 155 fs. Moreover, the reference spur is less than −60 dBc/Hz.

A new design for programmable logic array based on QCA-based nanotechnology

Dissipation in the complementary metal-oxide-semiconductor circuit size range has become a challenge for designers seeking to create a circuit with low power consumption and significantly reduced size. As a result, there is a need for an alternative technology that may provide revolutionary results. The quantum-dot cellular automaton is now widely regarded as a viable alternative to complementary metal-oxide-semiconductor technology. This paper demonstrates a new circuit for constructing a quantum-dot cellular automaton-based programmable logic array. The programmable logic array is a promising, standard, and fully programmable architecture that can use redundancy to make circuits with nanoscale feature sizes more practical. The comparisons based on cell number, size, and clock phases were made between the proposed circuit and previous ones using the QCADesigner. These comparisons verified the efficiency of the proposed design. The suggested programmable logic array circuit consists of 26 cells and occupies 0.04 µm2. In addition, the quantum cost of this circuit is 2.08, and the area delay is 0.08.

Photic Entrainment of the Circadian System.

Circadian rhythms are essential for the survival of all organisms, enabling them to predict daily changes in the environment and time their behaviour appropriately. The molecular basis of such rhythms is the circadian clock, a self-sustaining molecular oscillator comprising a transcriptional–translational feedback loop. This must be continually readjusted to remain in alignment with the external world through a process termed entrainment, in which the phase of the master circadian clock in the suprachiasmatic nuclei (SCN) is adjusted in response to external time cues. In mammals, the primary time cue, or “zeitgeber”, is light, which inputs directly to the SCN where it is integrated with additional non-photic zeitgebers. The molecular mechanisms underlying photic entrainment are complex, comprising a number of regulatory factors. This review will outline the photoreception pathways mediating photic entrainment, and our current understanding of the molecular pathways that drive it in the SCN.

Real-Time Precise Orbit Determination for LEO between Kinematic and Reduced-Dynamic with Ambiguity Resolution

The real-time integer-ambiguity resolution of the carrier-phase observation is one of the most effective approaches to enhance the accuracy of real-time precise point positioning (PPP), kinematic precise orbit determination (KPOD), and reduced-dynamic precise orbit determination (RPOD) for low earth orbit (LEO) satellites. In this study, the integer phase clock (IPC) and wide-lane satellite bias (WSB) products from CNES (Centre National d’Etudes Spatiales) are used to fix ambiguity in real time. Meanwhile, the three models of real-time PPP, KPOD, and RPOD are applied to validate the contribution of ambiguity resolution. Experimental results show that (1) the average positioning accuracy of IGS stations for ambiguity-fixed solutions is improved from about 7.14 to 5.91 cm, with an improvement of around 17% compared to the real-time float PPP solutions, with enhancement in the east-west direction particularly significant, with an improvement of about 29%; (2) the average accuracy of the estimated LEO orbit with ambiguity-fixed solutions in the real-time KPOD and RPOD mode is improved by about 16% and 10%, respectively, with respect to the corresponding mode with the ambiguity-float solutions; (3) the performance of real-time LEO RPOD is better than that of the corresponding KPOD, regardless of fixed- or float-ambiguity solutions. Moreover, the average ambiguity-fixed ratio can reach more than 90% in real-time PPP, KPOD, and RPOD.

A Clock-Phase Reuse Technique for Discrete-Time Bandpass Filters

In this article, we apply a new clock-phase reuse technique to a discrete-time infinite impulse response (IIR) complex-signaling bandpass filter (BPF). This leads to a deep improvement in filtering, especially the stopband rejection, while maintaining the area, sampling frequency, and the number of clock phases and their pulsewidths. Fabricated in 28-nm CMOS, the proposed BPF is highly tuneable and is capable of achieving a 70-dB stopband rejection at 50-MHz offset with 25% duty-cycle clocks while consuming 1.65 mW. The achieved in/out-of-band third-order intermodulation intercept point (IIP3) is +2.5 dB and +17.3 dBm, respectively, and the input-referred noise (IRN) is 1 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${\mathrm {nV}}/{\sqrt {\mathrm{ Hz}}}$ </tex-math></inline-formula> .

A high precision phase measurement system implemented in FPGA with phase interpolator.

High precision timing distribution is crucial to many large scale cosmology and particle physics experiments. Besides the space and energy information, the accurate timing provides an extra dimension for physics event reconstruction. In the timing distribution system, accurate clock phase measurement is an indispensable tool to monitor the phase drift and to achieve accurate phase adjustment. This paper introduces a novel phase measurement method implemented in the Xilinx Field Programmable Gate Array (FPGA). It uses the dedicated phase interpolator in the multi-gigabit transceiver. A design based on this method is implemented within the Kintex Ultrascale series FPGA. The preliminary test result shows that a sub-picosecond level precision is achieved. With this system, the nonlinearity of the phase adjustment in the Xilinx transceiver is measured.

Phase Noise Analysis of Clock Generator by Using Phase Noise Sensitivity

Phase noise represents signal instabilities in the frequency domain and is assessed through power measurements at various offsets from the carrier frequency. Herein, the phase noise of a clock generator is analyzed and modeled. Sources for the phase noise of the clock output at the resonance frequency are identified, including the power supply, the heat sink, and the external crystal. Low-frequency resonance is detected and validated to be caused by the external crystal grounding design. Solutions to decrease crystal-related noise are proposed and validated. In addition, the sensitivity based on the signal-to-noise ratio is proposed and verified with measurements, to numerically analyze the effects of power supply noise on clock phase noise. The proposed phase noise sensitivity is extracted from the measured phase noise results and can be used to estimate the phase noise and jitter of different power supply noises. The extraction and prediction method are validated with different buffer types including LVDS, HCSL, LVPECL, and LVCMOS in a device under test with the given design.

Power optimization in TSPC D flip-flop based 4-bit counter

In the present communication, the basic D flip flop has been considered with TSPC (True Single Phase Clock) logic for designing a novel 4-bit counter on 45 and 32nm technology. Here, it was with average power of 309 μWatts and 166.8 μWatts, which is very high on the respective technologies. The challenge is to reduce the average power and off state leakage power. To consider the challenge, two different techniques have been considered for power saving as, sleeping transistors and technique, modified TSPC D flip-flop (modified version In comparative study of simulations, it is observed that employing modified version of TSPC D flip-flop shows the most optimum results in terms of propagation delays and average power. Average power has been obtained as 260.3 μWatts which is 15.76% less than base counter on 45nm technology, and 133.2 μWatts which is 20.14 % less on 32nm technology. Moreover, Transistor sizing has also been used for separate analysis in which case the average power consumption has been found most minimum in 6/4 aspect ratio as 196.6 μWatts and 70.31 μWatts in both technologies respectively, among 6/4, 5/3 and 4/2 ratios.

Two-Time Procedure for Calculation of Carrier Frequency of Phasomodulated in Communication Systems

The use in radio communication systems of phase modulation of a signal intended for the transmission of useful information in a continuous mode creates the problem of frequency uncertainty of the received signal by frequency.In practice, it is not possible to implement frequency estimation in the conditions of chat uncertainty of the signal in the channel with low energy of the signal received in the continuous mode. Therefore, the estimation of the carrier frequency offset of the signal received relative to the nominal value is carried out before other synchronization procedures are included, namely: phase synchronization and clock synchronization. The paper generalizes the procedure and forms a two-step procedure for calculating the carrier frequency of the phase-modulated signal of a radio communication system for data transmission in a continuous mode, taking into account the condition of uncertainty of all signal parameters. Achieving the minimum observation interval in the given order of calculation of the carrier frequency is ensured by the use of the fast Fourier transform function. In order to analyze the effectiveness of this procedure, the process of estimating the carrier frequency of the phase-modulated signal of the radio communication system during data transmission in continuous mode and functional dependences of the maximum frequency in the signal spectrum and the minimum variance of carrier frequency estimation. This procedure allows a two-stage assessment of the carrier frequency according to the rule of maximum likelihood, taking into account the condition of uncertainty of all parameters of the signal received by the satellite communication system in a continuous mode with a minimum observation interval. Achieving the minimum observation interval in the given order of carrier frequency estimation is ensured by using the fast Fourier transform function and two estimation steps. The analysis of the efficiency of the estimation of the specified order was carried out on the basis of comparison of a ratio of the received minimum variance of an estimation of a carrier frequency and theoretically possible border of the minimum variance.

Experimental Evaluation of Sub-Sampling IQ Detection for Low-Level RF Control in Particle Accelerator Systems.

The low-level radio frequency (LLRF) control system is one of the fundamental parts of a particle accelerator, ensuring the stability of the electro-magnetic (EM) field inside the resonant cavities. It leverages on the precise measurement of the field by in-phase/quadrature (IQ) detection of an RF probe signal from the cavities, usually performed using analogue downconversion. This approach requires a local oscillator (LO) and is subject to hardware non-idealities like mixer nonlinearity and long-term temperature drifts. In this work, we experimentally evaluate IQ detection by direct sampling for the LLRF system of the Polish free electron laser (PolFEL) now under development at the National Centre for Nuclear Research (NCBJ) in Poland. We study the impact of the sampling scheme and of the clock phase noise for a 1.3-GHz input sub-sampled by a 400-MSa/s analogue-to-digital converter (ADC), estimating amplitude and phase stability below 0.01% and nearly 0.01°, respectively. The results are in line with state-of-the-art implementations, and demonstrate the feasibility of direct sampling for GHz-range LLRF systems.