A 48 GHz Fundamental Frequency PLL with Quadrature Clock Generation for 60 GHz Transceiver

Xiaokang Niu,Long He,Xu Wu,Depeng Cheng,Dongming Wang,Lianming Li

doi:10.3390/electronics11030415

Xiaokang Niu, Long He + Show 4 more

Open Access

https://doi.org/10.3390/electronics11030415

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Journal: Electronics	Publication Date: Jan 29, 2022
Citations: 3	License type: CC BY 4.0

Affiliation: Southeast University, Purple Mountain Laboratories

Abstract

This paper presents a design of a 48 GHz CMOS phase-locked loop (PLL) for 60 GHz millimeter-wave (mmWave) communication systems. For the sliding intermediate frequency (sliding-IF) transceiver applications, a fundamental frequency PLL with quadrature clock generation scheme is proposed. Specifically, with an implicit capacitive-bridged shunt peaking network, a second order harmonic filtering technique is realized in the voltage control oscillator (VCO) to broaden the bandpass response, thereby avoiding the complex common-mode resonant tank calibration and improving the phase noise performance. A robust current mode logic (CML) static frequency divider topology is adopted to realize the prescaler and to generate the quadrature clock. With the capacitive-bridged shunt peaking load and robust biasing circuit, the static frequency divider locking range and high frequency performance is improved and its reliability is enhanced over the PVT corners. To improve the image suppression ratio of the transceiver, a quadrature clock phase calibration scheme is proposed and verified. Fabricated in a 65 nm CMOS process, the PLL occupies a core area of 800 μm × 950 μm. Over the frequency range of 45.2 to 52.6 GHz, the measured PLL in-band phase noise PLL is better than −90 dBc/Hz@100 KHz offset, and its jitter is less than 155 fs. Moreover, the reference spur is less than −60 dBc/Hz.

Highlights

With the wide bandwidth nature, the unlicensed 60 GHz band is considered as a solution for the several short distance and high data rate applications, such as wireless backhaul, augmented reality (AR), and virtual reality (VR)
With a 108 MHz reference clock, by tuning division ratio of the multi-modulus dividers (MMD) circuit, four typical clock frequencies (46.656, 48.384, 50.112, and 51.840 GHz) are generated, which correspond to four channel center frequencies of the 60 GHz band
Benefiting from the above-mentioned design techniques of the voltage control oscillator (VCO) and frequency divider, the phase-locked loop (PLL) can cover the four channels of the 60 GHz band, and the in-band phase noise is better than −90 dBc/Hz at 100 KHz offset

Summary

Introduction

With the wide bandwidth nature, the unlicensed 60 GHz band is considered as a solution for the several short distance and high data rate applications, such as wireless backhaul, augmented reality (AR), and virtual reality (VR). In [10], based on 20 GHz PLL and a 60 GHz sub-harmonic quadrature injection locked oscillator, a 60 GHz frequency synthesizer was realized in a 65 nm CMOS, achieving a phase noise of −96 and −117 dBc/Hz at 1 MHz and 10 MHz offset, respectively, at the cost of a large power consumption of the calibration loop. In [15], based on the reference sampling and injection-locked VCO (ILO) topology, a two stage 35 GHz mmWave frequency synthesizer was realized with a 45 nm CMOS process, achieving 251 fs rms jitter. By introducing an implicit capacitive-bridged shunt peaking network, a broadband second order harmonic filter is realized in the VCO, thereby relaxing its common-mode resonant tank calibration issues and improving the phase noise performance.

Proposed PLL Topology for the 60 GHz Sliding-IF Transceiver

VCO Implementation

Frequency Dividers Implementation

D DB CK CKB

Quadrature Clock Calibration

Measurement Results

Conclusions