Phase Noise Performance Research Articles

Low-Phase-Noise Tenfold Frequency Multiplication Based on Integrated Optical Frequency Combs

We experimentally demonstrate a low-phase-noise tenfold frequency multiplier based on a compact integrated optical frequency comb (OFC) generator. The Indium Phosphide (InP) monolithically integrated OFC is based on a flexible scheme using cascaded optical modulators. The extremely compact frequency multiplier is broadly tunable in wavelength and in OFC repetition frequency, making it interesting for high-spectral-purity mm-waves applications. OFC generation with a 2.6 GHz spacing and 19 tones within a 10 dB power range and an optical signal-to-noise ratio (OSNR) higher than 40 dB is reported. Using a 74 GHz-bandwidth photodetector, we achieve a set of 2.6 GHz phase-stabilized electrical tones, reaching carriers up to 39 GHz with a high signal-to-noise ratio (SNR). In particular, the OFC-based tenfold-multiplied signal (26 GHz) provides a remarkable low-phase-noise feature, equivalent to the commercially available radiofrequency (RF) generator used as a source at the same electrical power. At 26 GHz, phase-noise of −50 dBc/Hz and −80 dBc/Hz are reported for 10 Hz and 1 kHz offsets, respectively. The proposed system enables frequency multiplication up to 12-times without phase impairments, i.e., phase noise performance equivalent to a commercial RF generator, validating its potential to low-phase-noise and high-spectral-purity mm-wave applications.

Improved Phase Noise Performance of PFD/CP Operating in 1.5 MHz– 4.2 GHz for Phase-Locked Loop Application

Improved Phase Noise Performance of PFD/CP Operating in 1.5 MHz– 4.2 GHz for Phase-Locked Loop Application

Optoelectronic oscillator with improved sidemode suppression by joint use of spectral Vernier effect and parity-time symmetry.

An optoelectronic oscillator (OEO) with improved sideband suppression by joint use of the spectral Vernier effect and parity-time (PT) symmetry is proposed and experimentally demonstrated. The spectral Vernier effect is implemented using two mutually coupled loops with different loop lengths, to increase the effective free spectral range (FSR). To further increase the mode selection capability to ensure stable single-frequency oscillation with an increased sidemode suppression ratio (SMSR), PT symmetry is implemented, in which the two mutually coupled loops are controlled with balanced gain and loss. Thanks to the combined effects, stable single-mode oscillation with a significantly increased SMSR is achieved. The proposed OEO is studied theoretically and evaluated experimentally. The results show that for a generated microwave signal at 10 GHz, the SMSR is 67.68 dB, which is increased by 11.20 dB or 26.05 dB, when using only the spectral Vernier effect or only the PT symmetry. Thanks to the long length of the longer loop, good phase noise performance is still maintained. The measurement shows that a phase noise as low as -124.5 dBc/Hz at an offset frequency of 10 kHz is achieved.

Enhancement of Accuracy of mm-Wave Vital Sign Radar Using Polar Cross Correlation and Low-Noise mm-Wave Frequency Synthesizer

The accuracy of a radar for sensing vital signs is generally affected by system noise, including the phase noise of the frequency synthesizer and the intermodulation of the vital sign signals. System noise becomes particularly serious when vital sign radars operate in the millimeter wave (mm-wave) band because the phase noise performance of mm-wave frequency synthesizers is generally inferior to that of microwave frequency synthesizers. To address the problem of system noise, a polar cross-correlation function (CCF) and a low-noise mm-wave frequency synthesizer were developed. The polar CCF can suppress both the intermodulation of vital sign signals and the phase noise of the radar system. The low-noise mm-wave frequency synthesizer further reduces the system phase noise by injection- and frequency-locked loop (IFLL) and loop bandwidth (BW) optimization. Experiments demonstrated that the proposed IFLL and loop BW optimization reduce the phase noise of a 24 GHz vital sign radar by more than 28 dB within the loop BW. The proposed polar CCF can further reduce the noise floor and intermodulation of the detected vital sign signals by 24 dB and 17 dB, respectively. These noise reductions reduced the standard deviation (SD) of the sensed respiration rate (RR) and heart rate (HR) by more than half, making the implemented 24 GHz vital signs radar system more reliable and accurate.

A Low-Power ADPLL with Calibration-Free RO-Based Injection-Locking TDC for BLE Applications

This paper proposes a low-power all-digital phase-locked loop (ADPLL) with calibration-free ring oscillator (RO)-based injection-locking time to digital converter (TDC) for BLE applications. The RO is reused as the delay cell of TDC, and the quantization step of TDC is always tracked with the RO period; hence no calibration is needed in this architecture. We adopt RO tuning to lower the injection-locking bandwidth so as to decrease the power consumption of the injection current. Moreover, the fractional part of phase error detection is turned down in the coarse tuning of ADPLL to save power. An LC-based digital-controlled oscillator (LCDCO) with a 6.4 nH inductor and a resistive bias is used to have a low power and better phase noise performance. The ADPLL is fabricated in 40 nm CMOS with a 1 V supply and consumes 1.4 mW when it is locked. The measured phase noise is −114 dBc/Hz at 1 MHz offset. The test results show significant power saving. Thus, it can be a promising candidate for BLE applications.

Effect of erbium-doped fiber amplifier loss compensation on 5G new radio millimeter-wave seamless transmission over analog fiber and free space optical fronthaul at 60 GHz

We demonstrate a fifth generation (5G) new radio (NR) signal transmitted by an analog optical and seamless antenna wireless connection at the frequency band of 60 GHz to exploit a high-frequency unlicensed frequency range. An optical frequency doubling technique, using two Mach–Zehnder modulators operating in a carrier suppressed and linear regime, respectively, was adopted to obtain the desired millimeter wave frequency at the photodetector’s output. The proposed system was tested with the 5G NR signals with a maximum bandwidth of 200 MHz and 64 quadrature amplitude modulation format. It was shown that the signal transmitted through the optical fiber and free space optical link with 1 m long seamless antenna transmission at 62 GHz was capable of meeting the signal quality requirements in terms of error vector magnitude. Moreover, the system phase noise performance showed an almost negligible difference between the various system configurations.

A 1.15-mW Low-Power Low-Complexity Reconfigurable FM-UWB Transmitter

A 1.15-mW 3.75–4.25-GHz frequency-modulated ultrawideband (FM-UWB) transmitter (TX) is fabricated in 65-nm CMOS, with digitally reconfigurable subcarrier frequencies, UWB bandwidth, and radio frequency (RF) frequency band. Low-complexity submodules are utilized with significant power savings. An ultralow-current hybrid module is for bandgap reference (BGR) and power-ON reset (POR), and a single-ended crystal oscillator (XO) generates a 12-MHz clock reference. A dual-path ring voltage-controlled oscillator (VCO) conducts linear RF FM, followed by a push–pull power amplifier (PA) for 100-kb/s wireless data transmission. A differential relaxation oscillator (OSC) is for subcarrier generation, and an intermittent dual-mode frequency calibration loop ensures system robustness. Experimental results show that the presented FM-UWB TX successfully generates an Federal Communications Commission (FCC)-compliant UWB signal, with an energy efficiency of 11.5 nJ/bit and an active area of 0.21 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> from a 1-V supply. The 2.25- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{A}$ </tex-math></inline-formula> hybrid BGR and POR achieves a temperature coefficient of 32 ppm/°C, a line regulation of 2.3%/V, a supply-ramp-rate-tolerant power-ON, and brown-out function. The 40- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{W}$ </tex-math></inline-formula> XO features a low-frequency inaccuracy of 4 ppm/V. The 40- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{A}$ </tex-math></inline-formula> relaxation OSC provides the reconfigured two-frequency shift keying (FSK) triangular amplitude and frequency. The 2.79–5.18-GHz 0.6-mW ring VCO is capable of providing the phase noise performance of −77 dBc/Hz at the 1-MHz offset, followed by the 0.45-mW PA having the output power higher than −14 dBm and the peak power-added efficiency (PAE) of 29.6%. All these benefit low-power low-cost TX implementation, where the carrier and subcarrier frequencies are calibrated by an intermittent digital loop with omitted power dissipation.

Even-Harmonic Class-E CMOS Oscillator

This article proposes the theory and implementation of an even-harmonic class-<inline-formula> <tex-math notation="LaTeX">$E$ </tex-math></inline-formula> CMOS oscillator that displays an excellent phase noise performance. Starting from zero voltage switching (ZVS) and zero derivative switching (ZDS) conditions, expressions for drain voltage and current waveforms are derived. Based on a 1:1 transformer, a custom-designed tank is proposed, which satisfies ZVS and ZDS conditions for the core transistors, provides high-<inline-formula> <tex-math notation="LaTeX">$Q$ </tex-math></inline-formula> resonances at both fundamental and second harmonics of the oscillation frequency, and yields a passive voltage gain from the drain to the gate of the core transistors. Satisfying ZVS and ZDS conditions reduces the overlap between the voltage and current waveforms of the transistor that increases the power efficiency of the oscillator. Furthermore, it widens the flat span of the semi half-sinusoidal voltage waveform, where the impulse sensitivity function (ISF) is negligible. Therefore, the conversion of the core transistor noise to phase noise is reduced. These features improve the oscillator&#x2019;s figure of merit (FoM) in comparison with state-of-the-art CMOS oscillators. The prototype of the even-harmonic class-<inline-formula> <tex-math notation="LaTeX">$E$ </tex-math></inline-formula> oscillator is implemented in a 0.18-<inline-formula> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> CMOS technology. At 4 GHz, it exhibits a phase noise of &#x2212;152.75 dBc/Hz at a 10-MHz offset while providing a 10.6% tuning range. The corresponding FoM is 197.9 dBc/Hz. The circuit draws 7 mA from a 0.7-V supply, and the die area is 0.23 mm².

Highly improved side mode suppression ratio and a low phase noise optoelectronic oscillator.

By adopting self-injection locking (SIL) technology in an external injection locking (EIL) optoelectronic oscillator (OEO), a highly improved side mode suppression ratio (SMSR) and low phase noise microwave signal generator is designed. The EIL ranging is closely related to the frequency spacing ranging of the free-running OEO, which is the reverse of the oscillation loop length, and limits the phase noise performance. Here SIL technology is introduced to significantly increase the Q-factor of the OEO without degrading the SMSR by setting the longer loop without oscillation. Both the simulation and experimental results are carried out to confirm the conclusion. Additionally, an SMSR up to 86 dB and phase noises as low as -88.80dBc/Hz@100Hz and -122.83dBc/Hz@10kHz, respectively, are demonstrated. Furthermore, the frequency overlapping Allan deviation of the proposed OEO scheme is also enhanced by 103 times, which benefits from the external injection technology compared with the free-running OEO. In addition, the SMSR and phase noise modification dependence on the fiber length, the RF source quality and external injection power, as well as the frequency tunability, are detailed and discussed to reveal the compatibility combination mechanism of the EIL and the SIL.

A 78.8-84 GHz Phase Locked Loop Synthesizer for a W-Band Frequency-Hopping FMCW Radar Transceiver in 65 nm CMOS.

A W-band integer-N phase-locked loop (PLL) for a frequency hopping frequency modulation continuous wave (FMCW) radar is implemented in 65-nm CMOS technology. The cross-coupled voltage-controlled oscillator (VCO) was designed based on a systematic analysis of the VCO combined with its push-pull buffer to achieve high efficiency and high output power. To provide a frequency hopping functionality without any overhead in the implementation, the center frequency of the VCO is steeply controlled by the gate voltage of the buffer, which effectively modifies the susceptance of the VCO load. A stand-alone VCO with the proposed architecture is fabricated, and it achieves an output power of 13.5 dBm, a peak power efficiency of 9.6%, and a tuning range of 3.5%. The phase noise performance of the VCO is −92.6 dBc/Hz at 1-MHz and −106.1 dBc/Hz at 10 MHz offset. Consisting of a third-order loop filter and a divider chain with a total modulus of 48, the locking range of the implemented PLL with the cross-coupled VCO is recorded from 78.84 GHz to 84 GHz, and its phase noise is −85.2 dBc/Hz at 1-MHz offset.

Low phase noise oscillator employing miniaturized shielded-EMSIW resonators embedded with CSRRs structure

In this paper, a parallel-feedback oscillator exploiting miniaturized shielded eighth mode substrate integrated waveguide (SD-EMSIW) resonators embedded with complementary split-ring resonators (CSRRs) structure is proposed. The phase noise performance of the designed oscillator can be efficiently enhanced by employing the SD-EMSIW resonators. Meanwhile, the physical size is prominently miniaturized by loading the CSRRs. The proposed oscillator is designed at 3.5 GHz by utilizing a four-order quasi-elliptic bandpass filter (BPF), combining the shielding metallized walls and etched CSRR techniques on the EMSIW cavities. The proposed prototype has been designed, fabricated and experimented. The experimental results indicate that the oscillator operates at 3.52 GHz with an output signal of 4.2 dBm. The second-harmonic suppression reaches to 25.2 dBc. The phase noise performance of the proposed oscillator features −134.8 dBc/Hz at 1-MHz frequency-offset. In addition to the property of the low phase noise, the proposed prototype exhibits the merits of miniaturized dimension and effective shielding characteristic.

A 3-GHz Inverse-Coupled Current-Reuse VCO Implemented by 1:1 Transformer

A voltage-controlled oscillator (VCO) based on a current-reuse (CR) topology is proposed. By inversely coupling two CR VCOs through tank inductors, the proposed VCO inherits the good phase noise performance of CR VCO, and meanwhile can realize differential outputs and alleviate the disturbance of VCO to the power supply and ground. Also, the proposed VCO achieves a phase noise improvement due to the electro-magnetic coupling of a transformer. Fabricated in the 180-nm CMOS process, the core circuit of the proposed VCO occupies an area of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$0.4\times0.32$ </tex-math></inline-formula> mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . Under a supply voltage of 1.2 V, the measured tuning range is 2.88–3.61 GHz (22.5%). The phase noise at 1-MHz offset varies between −126.7 and −123 dBc/Hz among the tuning range. The figure of merit (FoM) is in the range of 188.1–190.7 dBc, at 1-MHz offset.

X‐ and Ku‐ bands wideband low‐noise phase‐locked loop in 0.13 μm SiGe BiCMOS technology

This paper presents a 9.4 ~ 20.6 GHz low-noise phase-locked loop (PLL) in 0.13-μm SiGe BiCMOS technology for 5G applications. To achieve the wideband and phase noise performance simultaneously, a four-core Colpitts voltage-controlled oscillato array with 2-bit switched capacitors and 2-bit-control bias currents is used in the PLL loop. In order to optimize the programmable frequency divider accurately, the injection-locking behavior model of the dual-mode prescaler is quantitatively analyzed, which is proved to be effective through the tape-out. The fabricated proposed PLL achieves the average phase noise of −100.5 dBc/Hz at 1-MHz offset, wideband locking range of 74.7% and the high FOMT of 183.3 dBc/Hz. It occupies an area of 8.4 mm2, and its maximum power consumption is 319.7 mW.

High-gain narrowband radio frequency signal amplifier based on a dual-loop optoelectronic oscillator.

A novel photonic-assisted method for radio frequency (RF) signal amplification with high-gain and narrowband based on a dual-loop optoelectronic oscillator (OEO) is proposed and experimentally demonstrated. In the proposed system, the low-power RF signal is injected into a dual-loop OEO which is below the threshold oscillation state. And the maximum gain is obtained when the frequency of the RF signal matches with the potential oscillation mode of the dual-loop OEO. The approach provides an average gain greater than 22 dB for the RF signal which matches with oscillation mode. After amplification, the signal-to-noise ratio (SNR) turns out to be 40 dB. Furthermore, the 3 dB bandwidth of the suggested system can be narrower than 1.2 kHz which can effectively remove the out-of-band noise and spurious effects. Meanwhile, the performance of sensitivity and phase noise are also investigated.

A Differential Ring Oscillator With Tail Current Source Control Scheme Using N-Type Oxide TFTs

In this article, a voltage-controlled oscillator (VCO) design using n-type metal oxide thin-film transistor (TFT) technology is proposed. The VCO has a differential structure delay cell based on a tail current source control scheme. The circuits were fabricated on a glass substrate using our ITO-stabilized ZnO TFT technology. According to tape-out test results, under a 15-V power supply voltage, the presented VCO can reach a 111.23–171-kHz tuning range, a 4.28-kHz/V tuning sensitivity, and 4% linearity error. When the control voltage changes from 2 to 15 V, the VCO gain range is 177.5–181.9 kHz/V. The phase noise performance was also analyzed. At 150 kHz, the phase noise of the VCO is −74.5 dBc/Hz at a frequency offset of 340 kHz. In addition, the circuit power consumption at the maximum oscillation frequency is 1.5 mW. These results indicate that the VCO can be applied to transparent and flexible sensors and digital signal processor (DSP) electronics with moderate speed requirements.

Self-Injection-Locked Optoelectronic Oscillator Based on Frequency Conversion Filtering

The multi-mode noise is an important issue for the optoelectronic oscillator (OEO) in generating a spectrally pure microwave. Especially in oscillators with low phase noise, increasing the cavity length to improve the phase noise performance will make the mode interval smaller, which is more likely to cause multi-mode noise. Here, we proposed a low phase noise and high side-mode suppression ratio self-injection-locked OEO based on frequency conversion filtering. We theoretically and experimentally studied the influence of the phase noise of the external microwave source on the proposed OEO and, as a comparison, the conventional injection-locked OEO. The results show that, compared with the traditional injection-locked OEO, the proposed OEO is less sensitive to the phase noise of the external microwave source. Under the same experimental conditions, the proposed OEO achieved the same side-mode suppression ratio and the phase noise is reduced by 30 dB at 10 kHz offset from the 10-GHz carrier compared with the conventional injection-locked OEO.

Polarization-insensitive coupled optoelectronic oscillator with low spurious tones and phase noise

A coupled optoelectronic oscillator (COEO) based on σ-shaped fiber ring structure and intra-cavity semiconductor optical amplifier (SOA) is proposed and experimentally demonstrated. The σ-shaped fiber ring structure is skillfully utilized in COEO to eliminate the harmful influence of polarization disturbance. The SOA is embedded for super-mode suppression due to the fast gain saturation effect. The eximious phase noise performance of COEO could be maintained by operating the SOA at the unitary gain regime. The stable operation of COEO is guaranteed by the immunity to polarization fluctuation and the greatly suppressed spurious-mode competition. As a result, a 10-GHz signal is generated featuring high spectral purity and ultra-low spurious tones as soon as the system is power-on, and can hold steady even if the polarization changes dramatically. The single sideband phase noise of the proposed COEO is about -133 dBc/Hz at 10-kHz offset frequency, and the spurious suppression ratio reaches more than 95 dB, which is 60-dB superior than the conventional COEO.

A Compact 0.2–0.3-V Inverse-Class-F23 Oscillator for Low 1/f 3 Noise Over Wide Tuning Range

We introduce a new mode of oscillation in an <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">LC</i> -tank: an inverse class-F <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">23</sub> . In contrast to the conventional class-F oscillators, in which a high value of the real impedance (i.e., resistance) is presented to the third (in class-F <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> ) or/and to the second (in class-F <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> /class-F <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">23</sub> ) oscillator harmonics via an auxiliary resonance, here low resistive impedances (resembling a non-ideal short) are presented at both the second and third harmonics. This is made possible by tight magnetic coupling in the differential and common modes, respectively, afforded by a new compact 2:3 transformer. Being largely free from the harmonics in the voltage waveform and their possible deleterious phase shift effects on the flicker noise up-conversion, the phase noise performance in the flicker and thermal regions is further improved by narrowing the conduction angle. The 2:3 step-up transformer also provides a high passive gain to help with the startup in face of low supply. The switched-capacitor banks and cross-coupled transistor pair are carefully integrated under the transformer with a special arrangement of native (high-resistivity) substrate layer to mitigate their effect on the oscillation while reducing the area by 30%. The proposed digitally controlled oscillator (DCO) is implemented in 28-nm CMOS and achieves −95 dBc/Hz and −118 dBc/Hz at 100 kHz and 1 MHz offsets, respectively, while operating at a 0.3 V supply. The measured <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$1/f^{3}$ </tex-math></inline-formula> corner stays within 60 to 100 kHz over the 35% tuning range (TR) (from 2.02 to 2.87 GHz). This results in a figure-of-merit (FoM) with normalized TR (FoM <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> ) of −196 and −199 dB at 100 kHz and 1 MHz offsets, respectively, is a record in the space of ≤0.5 V and ≤1 mW.

Performance Analysis of Ring Oscillators and Current-Starved VCO in 45-nm CMOS Technology

Abstract: This paper presents a relative study among two Ring oscillators architecture (CMOS, NMOS) and current-starved Voltage-controlled oscillator (CS-VCO) on the basis of different parameters like power dissipation ,phase noise etc. All the design has been done in 45- nm CMOS technology node and 2.3 GHz Centre frequency have been taken for the comparison because of their applications in AV Devices and Radio control. An inherent idea of the given performance parameters has been realize by thecomparative study. The comparative data shows that NMOS based Ring oscillator is good option in terms of the phase noise performance. In this study NMOS Ring Oscillator have attain a phase noise -97.94 dBc/Hz at 1 MHz offset frequency from 2.3 GHz center frequency. The related data also shows that CMOS Ring oscillator is the best option in terms of power consumption. In this work CMOS Ring oscillator evacuatea power of 1.73 mW which is quite low. Keywords: Voltage controlled oscillator (VCO), phase noise, power consumption, Complementary metal-oxide-semiconductor (CMOS), Current Starved Voltage-Controlled Oscillator (CS- VCO), Pull up network (PUN), Pull down network (PDN)

A 48 GHz Fundamental Frequency PLL with Quadrature Clock Generation for 60 GHz Transceiver

This paper presents a design of a 48 GHz CMOS phase-locked loop (PLL) for 60 GHz millimeter-wave (mmWave) communication systems. For the sliding intermediate frequency (sliding-IF) transceiver applications, a fundamental frequency PLL with quadrature clock generation scheme is proposed. Specifically, with an implicit capacitive-bridged shunt peaking network, a second order harmonic filtering technique is realized in the voltage control oscillator (VCO) to broaden the bandpass response, thereby avoiding the complex common-mode resonant tank calibration and improving the phase noise performance. A robust current mode logic (CML) static frequency divider topology is adopted to realize the prescaler and to generate the quadrature clock. With the capacitive-bridged shunt peaking load and robust biasing circuit, the static frequency divider locking range and high frequency performance is improved and its reliability is enhanced over the PVT corners. To improve the image suppression ratio of the transceiver, a quadrature clock phase calibration scheme is proposed and verified. Fabricated in a 65 nm CMOS process, the PLL occupies a core area of 800 μm × 950 μm. Over the frequency range of 45.2 to 52.6 GHz, the measured PLL in-band phase noise PLL is better than −90 dBc/Hz@100 KHz offset, and its jitter is less than 155 fs. Moreover, the reference spur is less than −60 dBc/Hz.