X‐ and Ku‐ bands wideband low‐noise phase‐locked loop in 0.13 μm SiGe BiCMOS technology

Abstract

This paper presents a 9.4 ~ 20.6 GHz low-noise phase-locked loop (PLL) in 0.13-μm SiGe BiCMOS technology for 5G applications. To achieve the wideband and phase noise performance simultaneously, a four-core Colpitts voltage-controlled oscillato array with 2-bit switched capacitors and 2-bit-control bias currents is used in the PLL loop. In order to optimize the programmable frequency divider accurately, the injection-locking behavior model of the dual-mode prescaler is quantitatively analyzed, which is proved to be effective through the tape-out. The fabricated proposed PLL achieves the average phase noise of −100.5 dBc/Hz at 1-MHz offset, wideband locking range of 74.7% and the high FOMT of 183.3 dBc/Hz. It occupies an area of 8.4 mm2, and its maximum power consumption is 319.7 mW.