Phase Margin Research Articles

Optimal Control Approach to Design a Three-Loop Autopilot for a Tactical Missile

Conventionally, the Three-Loop Autopilot is dominated by three main parameters namely the damping factor, time constant and the open-loop crossover frequency, to achieve the desired performance. In developing the autopilot gains, the same gains as the conventional approach can also be obtained using the general optimality theory. The basic idea of setting the design parameters and the feedback gains using methods of optimal control revolves around the proper selection of the performance index for which the control is optimized. In this paper, an explicit formula for autopilot gains is driven by taking into account the relations between the desired performance and the open-loop frequency, phase margin and time constant without the need to adjust the LQR weights. Since each set of design parameters selection doesn’t guarantee the existence of the optimal control law, the optimization criteria for the three-loop autopilot are derived to know the set of design parameters for which the control is optimized. Finally, an optimal criterion to select the design parameters and therefore the autopilot gains is developed, where the time constant is set to the designer objective while the open-loop crossover frequency and the phase margin as design constraints.

Design and simulation optimization of phase-locked loop structure for phase-shifting power supply

A phase-locked loop (PLL) of a phase-shifting power supply for the power system is designed in this paper. Taking the industrial frequency current as the reference signal, the input and output characteristics of the phase-frequency detector with charge pump are analyzed. In addition, the transfer function of the PLL system is analyzed by combining the passive second-order low-pass filter and the voltage-controlled oscillator. As a result, the influence of parameters such as charge pump current, phase margin, and loop bandwidth on the performance of the PLL is investigated, and the optimal parameters of each section are obtained. The results show that the optimized PLL has a locking time of 0.75 s, a pull-out range of 63.16 Hz, and a locking range of 43.82 Hz, with high stability and noise immunity.

A Digital Proportional–Resonant Controller With Desired Tracking-Error Convergence

Proportional-resonant (PR) controllers were initially presented within a continuous-time control framework; hence, their digital implementations may be susceptible to resonant-frequency offset and modulation-signal computational delay. Consequently, engineers may need to tune the controller parameters by trial and error to design the control systems that achieve desired performance. In digital control, sinusoidal references of power converters are discrete-time sequences. Based on this, we present a digital design technique for the PR controllers and demonstrate the design process using a 13.2-kW grid-connected inverter prototype. The design ensures the sinusoidal reference's tracking-error sequence converges at the desired rate. The advised design technique's merits include: 1) The tracking-error convergence rate, phase margin, and cut-off frequency have clear mathematical relations, allowing engineers to uniquely determine the controller parameters by specifying any two indicators. 2) With the tuned controller parameters, the tracking-error sequence can converge at the desired rate. 3) The resultant controller can be partitioned into one proportional term and two resonant terms; the first two terms are construed as a standard PR controller digitally implemented via the zero-order-hold method, whereas the second resonant term guarantees the tracking-error sequence converging in the desired manner. A case study results confirm the digital PR controller's efficacy.

Impedance remodeling control strategy of grid-connected inverter with inertia-damping phase-locked loop under extremely weak grid

The operation of the grid-connected inverter (GCI) in weak grid conditions presents a risk of instability due to the presence of high grid impedance and the negative impedance effect of the phase-locked loop (PLL). In response to this issue, this paper introduces an impedance remodeling control strategy for the GCI utilizing the inertia-damping phase-locked loop (ID-PLL). Firstly, the proposed ID-PLL exhibits certain inertia and damping properties in comparison to the traditional PLL (T-PLL), resulting in an enhanced phase margin of the GCI system's equivalent output impedance. Consequently, the adaptation range of the grid impedance increases from 12mH (SCR = 3.00) to 24mH (SCR = 1.37). Next, from the perspective of impedance analysis, this study remodels the PLL impedance and inverter control loop impedance, further improving the amplitude and phase margin of the system's output impedance. As a result, the adaptation range of the grid impedance extends to 33mH (SCR = 1.00), and the transition of grid-connected currents becomes smooth and free of overshoot. Finally, the effectiveness of the proposed control strategy is validated through theoretical analysis and experimental verification.

Analysis of super‐source‐follower‐based GHz‐bandwidth biquadratic low‐pass filters

SummaryThe design of GHz‐bandwidth super‐source‐follower‐based low‐pass filters (SSF‐LPFs) is investigated. The transfer function is derived by considering transistor parasitics. The behaviors of SSF‐LPFs can be predicted accurately with these formulas. The theoretical values of pole/zero frequencies of the circuit agree well with the corresponding simulation results. Moreover, the relationship between the Q factor and the phase margin of the biquadratic filter is revealed. Two 1.3‐GHz 4th‐order LPFs are designed using 90‐nm CMOS technology, where one contains a high‐Q biquad with a small phase margin and a low‐Q biquad, while the other is built with two biquads with moderate Q factors and sufficient phase margins. For the former, the discrepancy between the theoretical and simulated phase margin is <2°, and the discrepancy between the theoretical and simulated corner frequency is <6%. For the latter, the discrepancy between the theoretical and simulated phase margin is <4°, and the discrepancy between the theoretical and simulated corner frequency is <4%. The filter containing biquads with sufficient phase margins is fabricated and occupies an area of 0.44 mm2. Consuming 14.4 mW, the filter delivers a bandwidth of 1.3 GHz, P1dB of −11.94 dBm, and IIP3 of −4.5 dBm.

A dynamic optimal decoupling controller design for a multi-variable system with stability analysis: an algebraic approach

ABSTRACT This study describes the design and implementation of an algebraic approach for a dynamic optimal decoupling controller in a multi-variable liquid-level system. This method aligns with model-matching criteria and the frequency-matching technique. The prime objective of the proposed approach is to create a closed-loop feedback system using a PID controller that aligns with a user-defined linear system model in terms of both system dynamics and static behavioral response. To illustrate robust stability, the study incorporates multiplicative input and output uncertainty. Simulation results verify the efficacy of the proposed decentralized controller, presenting its effectiveness in achieving both set-point accuracy and disturbance attenuation. Furthermore, the study employs disk margin analysis to ascertain safe ranges for gain and phase margin.

Design, Simulation and Comparative Analysis of Two Stage Operational Amplifier Based on CNTFETs Using Indirect Feedback Frequency Compensation

In the course of this study, an efficient implementation of a high gain and low power two-stage operational amplifier using indirect feedback frequency compensation based on CNTFETs. HSPICE software was used to develop and simulate CNTFETs. The op-amps were designed using 0.9[Formula: see text]V input supply voltage. The proposed structures were formed either using CNTFETs only known as pure CNTFET-IFFC-2SOA or hybrid structures consisting a mix of both CNTFETs and conventional CMOS named as PCNTFET-NMOS-IFFC-2SOA and NCNTFET-PMOS-2SOA. The comparative investigation revealed that CNT-based structures performed significantly better than the traditional CMOS-based devices. In the instance of CNTFET-IFFC-2SOA, there was a considerable improvement in DC gain, power dissipation, phase margin, and CMRR. The DC Gain increased by 140.92%, the CMRR increased by 32.94%, and the phase margin increased by 4.9%. Furthermore, at the 32[Formula: see text]nm technology node, a GNRFET-based structure was designed and compared to conventional CMOS and pure CNTFET-based IFFC-2SOA. It was discovered that the DC gain, phase margin, and power dissipation obtained by the CNTFET-based structure were superior to both. The DC Gain of CNTFET-IFFC-2SOA was 156.79% more than that of GNRFET-IFFC-2SOA. To confirm the workability of the proposed circuits, an integrator was designed and simulated as its application. The CNTFET-based IFFC-2SOA integrators showed better integration action than the traditional CMOS-IFFC-2SOA.

A Comprehensive Stability Assessment System for EV DC Charging Station Based on Multitimescale Impedance Model

The existing all-in-one impedance-based stability analysis only qualitatively reveal the instability factors by the graphic Nyquist criterion while the stability margin is not considered. In this article, a design-oriented multiattribute and multidimensional based comprehensive assessment system (MAMD-CAS) is proposed to evaluate the stability quantitatively and guide the parameter design as well as ensure the desired dynamic response and stability margin. This MAMD-CAS mainly includes the loop-gain-based multi-timescale impedance estimation to analyze the low-frequency oscillation (LFO), phase margin (PM) calculation of different timescales and dynamic performance indicators as the time-domain quantitative expression of impedance estimation. In detail, the multi-timescale impedance model is established and its loop-gain representation is deduced to implement the impedance estimation. Combined with the known PM, the influence of the parameters on dynamic performance and stability margin can be comprehensively evaluated, then the conflict between dynamic performance and stability margin is explored. It is found that the voltage-loop parameters do not have the coupling problem between dynamic performance and stability margin while <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">J</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">vir</sub> and <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">k</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">svr</sub> present a conflicting effect between the inertia-loop LFO dynamic performance and stability margin and their interaction affects the severity of inertia-loop LFO. The appropriate control parameters can be thus selected for a good stability margin while suppressing the impedance peak. This MAMD-CAS analysis result is verified by simulation and experiment and this assessment system provides theoretical fundamental for the online stability monitor of multi-timescale power electronics system.

Distributed Minmax Strategy for Multiplayer Games: Stability, Robustness, and Algorithms.

This article studies a distributed minmax strategy for multiplayer games and develops reinforcement learning (RL) algorithms to solve it. The proposed minmax strategy is distributed, in the sense that it finds each player's optimal control policy without knowing all the other players' policies. Each player obtains its distributed control policy by solving a distributed algebraic Riccati equation in a multiplayer noncooperative game. This policy is found against the worst policies of all the other players. We guarantee the existence of distributed minmax solutions and study their L2 and asymptotic stabilities. Under mild conditions, the resulting minmax control policies are shown to improve robust gain and phase margins of multiplayer systems compared to the standard linear-quadratic regulator controller. Distributed minmax solutions are found using both model-based policy iteration and data-driven off-policy RL algorithms. Simulation examples verify the proposed formulation and its computational efficiency over the nondistributed Nash solutions.

SSA-based Fractional Order PI-PD Cascade Controller Design for DC Motor Speed Control

Bu çalışmada doğru akım (DA) motoru hız kontrolünü sağlamak için eklemeli ve kesir dereceli (FOPI-FOPD) denetleyici tasarımı önerilmiştir. Önerilen denetleyici parametreleri son yıllarda geliştirilen Serçe Arama Algoritması (SAA) ile optimize edilmiştir. Denetleyici parametrelerinin aranması için çeşitli amaç fonksiyonları kullanılmıştır. Bu amaç fonksiyonları zamanla çarpılan mutlak hatanın integrali (ITAE), mutlak hatanın integrali (IAE), zamanla çarpılan hatanın karesinin integrali (ITSE), hatanın karesinin integrali (ISE) ve Zwe-Lee Gaing (ZLG) fonksiyonudur. Zaman bölgesinde aşma (M_p), oturma süresi (t_s) ve yükselme süresi (t_r) bakımından kullanılan amaç fonksiyonlarından elde edilen sonuçlar karşılaştırılmıştır. Ayrıca elde edilen sonuçlar frekans bölgesinde kazanç marjı, faz marjı ve bant genişliği açısından incelenmiştir. Zaman ve frekans bölgesinde farklı amaç fonksiyonlarından elde edilen en iyi sonuç literatürdeki çalışmalarla karşılaştırılmıştır. Ayrıca önerilen denetleyicide elde edilen en iyi sonuç için gürbüzlük, bozucu yük ve referans hız değişimi analizleri incelenmiştir.

Design of carbon allotrope FET-based folded cascode operational transconductance amplifiers (FC-OTA)

ABSTRACT Throughout this study, a high-gain, low-energy folded cascode operational transconductance amplifier (FC-OTA) was modelled utilising HSPICE software. The FC-OTA designs included implementations availing CNFETs, GNRFETs, and mixed involving a combination of CNFETs with CMOS. Comparison with traditional CMOS-based FC-OTAs revealed that CNFET-based FC-OTAs exhibited considerable enhancements, displaying significant escalation in DC amplification, output resistance, average power dissipation, and CMRR. The phase margin in CNT-based FC-OTAs indicated stability. Moreover, CNT-based devices showed substantial rise in direct current amplification over GNRFET-FC-OTAs. The study further explored the operational effectiveness of proposed FC-OTAs by varying parameters such as CNT diameter, CNT pitch, and the number of CNTs, identifying optimal values that significantly enhance the FC-OTA’s performance. Comprehensive parametric and Monte Carlo analyses demonstrated OTA’s resilience to changes in supply voltage, temperature, capacitance, and mismatches. In summary, the folded cascode approach was found to enhance gain and reduce average power in CNFET-based FC-OTAs in comparison to other structural configurations.

A low‐power low‐dropout regulator with improved transient response and power supply rejection

SummaryA high‐precision fast‐settling low‐dropout (LDO) regulator has been presented in this paper. A novel frequency compensation scheme has been proposed to acquire wider bandwidth while sufficient stability is guaranteed for all loading conditions without using external compensation capacitors. Moreover, novel auxiliary circuits have been proposed to improve the slew rate and minimize the settling time. The new LDO has been designed in a standard 0.18‐μm CMOS process. Postlayout simulation results show that the LDO achieves 2.7‐ and 2.48‐MHz unity‐gain frequency for 100 and 0 mA of load current, respectively, while the minimum phase margin is 64°. The results also demonstrate that the worst‐case settling time is almost equal to 1.95 μs. It is shown that by using the new slew rate enhancement technique, the settling time has been reduced from 18 to 1.9 μs. The LDO consumes a quiescent current of 21.5 μA, and the power supply rejection is −46 dB at 10‐kHz offset, which makes the LDO capable of adequately suppressing input supply ripples. The large loop gain of the proposed circuit improves the accuracy of the LDO, and the load and line regulations are 0.1 mV/mA and 0.1 mV/V, respectively.

Design and Optimization of Voltage Mode PWM Control of DC-DC Buck Converter with a PI-Lead Compensator Using the Simulated Annealing Algorithm

This paper presents a method for improving the performance of DC-DC Buck Converter Systems using voltage mode Pulse Width Modulation (PWM) control. We explore the effectiveness of Proportional-Integral (PI) and Lead Compensator controllers in enhancing system stability, minimizing voltage fluctuations, and improving load response. The system is modeled through transfer functions, and the controllers' impacts are analyzed both individually and in tandem. A key contribution of this work is the optimization of the PI-Lead Compensator parameters utilizing the Simulated Annealing Algorithm, which is fine-tuned to improve phase margin, gain crossover frequency, and steady state error. These parameters are critical for optimizing the system’s output performance. Through MATLAB simulations, we demonstrate the iterative process of parameter optimization and validate the algorithm's efficacy in managing the DC-DC Buck Converter. The results highlight the enhanced performance achieved with the optimized parameters, providing a viable solution for effective control of DC-DC Buck Converter Systems.

Setting‐zero analysis for multistage amplifier design

SummaryA setting‐zero analysis method is presented to facilitate the prediction of zeros in multistage amplifiers. The main objective of this method is to simplify the analysis process of such amplifiers while improving the overall performance, and the feasibility is confirmed by various examples presented in this paper. By proposing a single‐capacitor cascode Miller compensation three‐stage amplifier using setting‐zero analysis, this paper has theoretically verified that the addition of a grounding second‐stage compensation capacitor is unnecessary. Measurement results show that this amplifier consumes a current of 38 μA at a 1.2 V supply voltage, with a 103 dB open‐loop gain. When driving a 1 nF load capacitor, this design achieves 1.88 MHz gain bandwidth and 73° phase margin, with a 3.33 V/μs average slew rate and an average 1% settling time of 0.40 μs under the unity‐gain configuration.

Artificial bee colony with predator effect algorithm for proportional integral derivative controller tuning

This paper proposes a novel artificial bee colony with predation effect (ABCPE) algorithm for tuning a proportional integral derivative (PID) controller. The mathematical model of ABCPE algorithm to introduce predator effect in the foraging behavior of artificial bees colony algorithm has been formulated. The proposed algorithm has been tested on tuning problems of different process models. The simulation results reveal that the closed-loop responses are relatively fast and non-oscillatory as compared to the frequency response analysis method for reference tracking. Further, the results obtained using ABCPE are also compared with other evolutionary algorithms. The exhaustive analysis shows that the ABCPE-based solution approach leads to a set of tuning parameters having smaller overshoot, less setting time, and rise time compared to other solution approaches. The stability analysis using Nichols plot reveals that the phase margin of proposed algorithm is higher as compared to other tuning methods. Finally, the convergence behavior and robustness analysis reveals the effectiveness of the proposed approach to solve engineering design problems.

A 65 nm CMOS rail-to-rail auto-zero operational amplifier based on charge pump internal power supply

A high-gain, low-offset, and low-power auto-zero operational amplifier with rail-to-rail input/output is proposed. Based on a time-interleaved charge pump high-voltage on-chip internal power supply, the PMOS differential pair input configuration will achieve a rail-to-rail input range with constant transconductance. Time-interleaved auto-zero continuously eliminates the input offset voltage of the operational amplifier in the time domain. An nA-level bias circuit to realize low power. The operational amplifier circuit is based on a 65 nm CMOS process. Under 1.2V power supply voltage and temperature 27 °C, the input offset voltage of the operational amplifier is 3.16 μV and the input offset current is less than 20 pA. The temperature drift coefficient of offset voltage is 0.005 μV/°C between −40 °C and 90 °C. The variation rate of input transconductance is only 5.6 % among the rail-to-rail input range. The equivalent DC gain is 106.4 dB, the unit gain bandwidth is 0.54 MHz, the phase margin is 76.5°, and the power consumption is about 0.19 mW. The layout area is 0.83 × 0.75 mm2.

Design and Implementation of C-Band Frequency Synthesizer Using LMX2592 IC

The paper presents the design scheme and implementation of a PLL-based-frequency synthesizer using LMX2592 IC. The frequency synthesizer have vital role in the development of up-converter and down-converter equipments. Therefore, on the RT-Duroid RO4350 substrate, a low phase noise and stable carrier generator is designed and implemented. Graphical User Interface (GUI) &amp; LAN based programming is developed to easily change the synthesizer frequency. The control system analysis using root locus and bode plot is presented for system stability.The experimental results representing the performance parameters, like frequency range, frequency step size, output power, phase noise, carrier stability, harmonics, and spurious, etc., are also presented in the paper. The analysis of spurious and phase noise performance at near integer boundary conditions are done by changing loop bandwidth and phase margin.

Fractional Order PID Control of Propofol Dosage and Optimization in Lean and Obese Patients

This paper outlines the design of a fractional-order proportional–integral–derivative controller for regulating the induction phase of Propofol infusion in lean and obese patients. The obtained controller is implemented within the pharmacokinetic-pharmacodynamic model and the nonlinear Hill function to conduct closed-loop simulations. The latter are employed using a dataset comprising 24 patients to obtain clinical evaluation results. The design of the controller relies on a generic second-order plus dead time approximation model, which characterizes interpatient variability in response to Propofol infusion within the studied population. The fractional-order proportional–integral–derivative is tuned to achieve sufficient robustness margins ie phase margin, cutoff frequency, and the consideration of the iso-damping properties. The results show no undershoot and a smooth convergence to the desired value of the bispectral index, which indicates the depth of hypnosis.

Robust FOPID Control of an After-Cooler Heat Exchanger with TES

In this paper the temperature control of an after-cooler heat exchanger (AHX) with Thermal Energy Storage (TES) is considered. The AHX can be modelled as a nonlinear system whose gain strongly depends on the operating point. This can cause the reduction of the phase margin which translates into the risk of excessive temperature overshoots. The generalized isodamping approach has been applied to design a fractional-order robust PID controller that guarantees the invariance of the phase margin despite the gain variations. Simulation results performed on a realistic model of the system demonstrate the effectiveness of the proposed design approach.

A Dual-Path Subsampling PLL With Ring VCO Phase Noise Suppression

This article presents a 2-GHz dual-path subsampling phase-locked loop (SSPLL) with ring voltage-controlled oscillator (VCO) phase noise suppression (PNS). In addition to the conventional subsampling charge pump (SSCP), a high-pass path from the subsampling phase detector (SSPD) to the low-pass filter (LPF) is implemented in the proposed SSPLL. Due to this dual-path architecture, a new in-band zero and pole are introduced into the open-loop transfer function (zero frequency is smaller than the pole frequency), which extends the open-loop unit-gain bandwidth without sacrificing the phase margin. Consequently, the phase noise contribution of the ring VCO is suppressed while the loop stability is ensured. Meanwhile, the phase noise contribution of the high-pass path is negligible compared to the reference and ring VCO’s contribution. Measurement results show that the SSPLL’s closed-loop bandwidth is extended to around 6 MHz with a reference of 20 MHz and the jitter is reduced by 1.34 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times$</tex-math> </inline-formula> (from 3.52 to 2.63 ps) with a maximum noise suppression of 6.5 dB at the 1.1-MHz offset. The PNS path consumes 0.16 mW and no delay line or calibration is needed, which results in a relatively high FoM <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$_{\mathrm{PNC}}$</tex-math> </inline-formula> value of 40.5 dB.