A 65 nm CMOS rail-to-rail auto-zero operational amplifier based on charge pump internal power supply

Abstract

A high-gain, low-offset, and low-power auto-zero operational amplifier with rail-to-rail input/output is proposed. Based on a time-interleaved charge pump high-voltage on-chip internal power supply, the PMOS differential pair input configuration will achieve a rail-to-rail input range with constant transconductance. Time-interleaved auto-zero continuously eliminates the input offset voltage of the operational amplifier in the time domain. An nA-level bias circuit to realize low power. The operational amplifier circuit is based on a 65 nm CMOS process. Under 1.2V power supply voltage and temperature 27 °C, the input offset voltage of the operational amplifier is 3.16 μV and the input offset current is less than 20 pA. The temperature drift coefficient of offset voltage is 0.005 μV/°C between −40 °C and 90 °C. The variation rate of input transconductance is only 5.6 % among the rail-to-rail input range. The equivalent DC gain is 106.4 dB, the unit gain bandwidth is 0.54 MHz, the phase margin is 76.5°, and the power consumption is about 0.19 mW. The layout area is 0.83 × 0.75 mm2.