Phase Margin Research Articles

Guidelines for Voltage Controller Coefficients Design to Attain Prescribed Grid Current THD and DC-Link Voltage Undershoot Values in Power Factor Correction Front Ends

This article establishes analytical guidelines for designing coefficients of proportional integral (PI) controller, typically used as voltage loop compensator of power factor correction rectifiers (PFCRs) operating in continuous conduction mode (CCM), based on two major performance merits (namely, total harmonic distortion (THD) of grid-side current and dc-link voltage deviation upon sudden load increase) and dc-link capacitance-to-rated power ratio. The proposed methodology allows to concretize the commonly used “5–10 Hz crossover frequency, 45°–70° phase margin” rule-of-thumb, typically used in application notes of commercial PFCR controllers. Explicit relationships between voltage loop gain crossover frequency and phase margin as well as settling time of dc-link voltage response to a step load increase to the above-mentioned performance merits are also derived in this article. Provided design guidelines allow to accurately achieve desired values of the two mentioned performance merits and indicate the feasible range of possible dc-link capacitance values. The proposed quantitative design guidelines are well-supported by experiments.

Design of chopper operational amplifier for leakage current protector chip

Due to the low frequency and small amplitude of the input signal of the leakage current protection chip, an operational amplifier with low offset and low power consumption is designed by using the chopper stabilization technique and the dynamic element matching technique. Based on the TSMC 0.18um process, the spectre environment in cadence is used for design and simulation. The power supply voltage is 1.8V. The post simulation results show that under the TT corner, the average current of the operational amplifier is 139uA, the loop gain is 85.9dB, the phase margin is 68.01°, and the power supply rejection ratio(PSRR) is 101.62dB@50Hz, the common mode rejection ration(CMRR) is 104.52dB@50Hz, the equivalent input noise is 129.86nv/sqrt(Hz)@50Hz, and the value of equivalent input offset voltage is 8.2uV(mean).

Research and experiment on control loop system of Source Measure Unit

Aiming at the problem that the capacitive load of the source measure unit (SMU) system affects the stability of the loop control, this paper makes an in-depth theoretical analysis of the loop control system based on the SMU. A theoretical and circuit model is established after the analysis. In the control loop structure, an integrator with proportional amplification serves as an error amplifier for the control loop system to obtain sufficient phase margin at the optimal bandwidth. A phase-lead compensation capacitor scheme is studied and proposed to achieve the maximum tolerance range to achieve the loop stability. The results show that the simulation and experimental results are basically consistent. The results verify the theoretical correctness and practical value of this SMU control loop system, and provide a theoretical basis for the research of the SMU control loop structure of the subsequent SIP process.

A New Stability Enhancement Method Using KF Estimation for the PWM-SMC-Based Grid-Tied Inverter Under Weak Grid Condition

A sliding-mode control (SMC) technology is widely used in inductor-capacitor-inductor (LCL)-filtered grid-tied inverters (GTIs) due to its strong robustness against parameter drift. However, under weak grid conditions, the steady performance of GTI using conventional pulsewidth-modulation-based SMC (PWM-SMC) degrades, resulting in increased harmonics in grid-injected currents. One reason is that the voltage feedforward term at the point of common coupling (PCC) in the SMC loop causes the phase margin of the inverter output impedance to decrease. Another reason is that the gain of conventional PWM-SMC-based systems is not high enough, especially under weak grid conditions. This article proposes a PCC feedforward voltage reconstruction method (named KF-PWM-SMC) for a PWM-SMC-based controller using Kalman filter (KF) estimation. As a result, the phase and magnitude of the inverter output impedance at the desired frequency can be significantly improved. Moreover, the proposed PCC feedforward voltage extraction method can save the PCC voltage control sensor, thereby improving the reliability of the whole system. A 3-kW experimental GTI based on the dSPACE DS1202 platform has been developed to verify the feasibility of the proposed control strategy.

Selection of PI + Notch Voltage Controller Coefficients to Attain Desired Steady-State and Transient Performance in PFC Rectifiers

The well-known trade-off between dc link voltage dynamics and ac-side current quality in power factor correction (PFC) rectifiers limits attainable dc link voltage loop bandwidth. It has been shown that adding a notch filter in series with the typically employed PI or type-II regulator allows improving dc link voltage dynamics without sacrificing total harmonic distortion (THD). However, clear quantitative guidelines for PI + Notch (PI + N) controller design to attain prescribed values of ac-side current THD and dc link voltage undershoot (response to a step-like load power increase) were not established so far. Consequently, analytical expressions linking the coefficients of the PI + N controller with the above-mentioned performance merits for a given value of dc link capacitance are revealed in this article. Corresponding dc link voltage loop gain phase margin and crossover frequency expressions are derived and the feasibility region of the proposed design guidelines is clearly indicated. Simulations and experimental results validate the proposed design methodology.

Frequency Compensation Network for Three-Stage CMOS Operational Amplifier

The rapid advancements of CMOS integrated circuits technologies lead designers to cascade structures and avoiding cascode amplifiers. As a result, frequency compensation becomes the most important issue since multi-stage amplifiers are highly potential to instability. Here in this work, two differential stages are exploited to form frequency compensation network. These stages realize four Miller loops and share each Miller capacitor in two loops simultaneously. This intensifies Miller effect to improve frequency response due to pole-zero cancellation. The proposed three stage amplifier is modeled symbolically via a transfer function (TF) while 0.18um CMOS technology is used for circuit simulation. Good agreement between theoretical calculation and simulation results shows validity and accuracy of the TF. Also ample simulations are performed to exhibit the proposed amplifier performance against parameters mismatches. The proposed three stage amplifier expresses 105 dB as DC-gain, 4.8 MHz as Gain Band Width and 72 degree as Phase Margin. The amplifier consumes 360 uW as power consumption. This performance obviously is an improvement of Nested Miller Compensation (NMC) while Figure of Merits (FoMs) are enhunced.

Frequency Domain Design Method of the Aeroengine Fuel Servo Constant Pressure Difference Control System with High Performance

The constant pressure difference regulating mechanism is widely used in aeroengine fuel servo metering systems, and it almost decides the metering precision. However, the design theory and design method of the available constant pressure difference regulating mechanism are unclear, and it is difficult to follow the high stability, high accuracy, and high robustness requirements of the modern aeroengine fuel servo metering system. In this paper, the design theory of the constant pressure difference regulating mechanism is revealed, and it indicates that it consists of two basic control units: a state feedback stabilization controller to ensure the asymptotic stability and disturbance rejection performance; and a servo and feed-forward compensator to ensure the asymptotic tracking ability. In addition, based on the frequency domain analysis method, the decisive influences about the control gains of the two control units on the dynamic performance and stability are analyzed. On this basis, a frequency domain design method of the two core control gains is proposed to complete the design task of the closed-loop system. The simulation results show that, under the adverse conditions of 1 MPa strong step disturbance of the inlet pressure and 50 mm2 strong step disturbance of the variable inlet flow area, the steady-state working range of the controlled pressure difference meets 0.92 ± 0.01 MPa, the steady-state error is not more than 1%, the regulation time is not more than 0.01 s, the dynamic overshoot is not more than 10%, and the designed phase margin is more than 70°.

Frequency Domain Specifications Based Robust Decentralized PI/PID Control Algorithm for Benchmark Variable-Area Coupled Tank Systems.

A decentralized PI/PID controller based on the frequency domain analysis for two input two output (TITO) coupled tank systems is exploited in this paper. The fundamentals of the gain margin and phase margin are used to design the proposed PI/PID controller. The basic objective is to keep the tank at the predetermined level. To satisfy the design specifications, the control algorithm is implemented for decoupled subsystems by employing a decoupler. First-order plus dead time (FOPDT) models are obtained for the decoupled subsystems using the model-reduction technique. In addition, the control law is realized by considering the frequency domain analysis. Further, the robustness of the controller is verified by considering multiplicative input and output uncertainties. The proposed method is briefly contrasted with existing techniques. It is envisaged that the proposed control algorithm exhibits better servo and regulatory responses compared to the existing techniques.

Robust tilt‐integral‐derivative controller synthesis for first‐order plus time delay and higher‐order systems

ABSTRACTA tilt integrator of the tilt‐integral‐derivative (TID) controller is an integrator to the power of a fraction. The current state of the art of TID controller is difficult to satisfy prespecified frequency‐domain specifications and is not able to build the connection between the frequency‐domain synthesis and time‐domain analysis. To fill the gap in TID control theory, a systematic tuning method of robust TID controller for first order plus time delay (FOPTD) and higher‐order processes is proposed, which is based on combining frequency‐ and time‐domain specifications synthesis. The TID controller parameters , , and optimal fractional order are settled to meet frequency‐domain specifications including phase margin, gain crossover frequency, and flat phase constraint that guarantee systemic stability and robustness. The parameter can be determined under the time‐domain specification including the smallest ITAE that achieves optimal dynamic performance. In addition, the steps of the proposed robust TID controller design process are given in detail, and an example is given to illustrate the corresponding steps. At last, the control and gain variation performances of the obtained TID controller are compared with some other controllers (PID, FOPI, and FOPID). Simulation results for FOPTD and higher‐order systems illustrate the superior robustness as well as the transient performance of the proposed control tuning procedure. To verify the practical usefulness of the outcomes of this paper, some experimental results on temperature control of a Peltier cell are presented.

Five‐stage CMOS OTAfrequency compensated via nested differential feedback

AbstractNowadays cascode structures or vertical arrangements of MOSFETs can not satisfy demands regarding high gain amplifiers. As a direct result, the only promising choice turns to Multi‐stage amplifiers via cascading gain stages. The challenge here is stability issues which shows itself by different frequency compensation. All problem starts with increasing number of nodes and consequent poles. The poles degenerate phase of system and need to be controlled. In this work, a five‐stage amplifier is targeted for a new and efficient frequency compensation technique. The major contribution of proposed approach is using only two Miller capacitors with considerable small values (10 pF) compared to load capacitor (500 pF). This achieved via exploiting two differential active stages which intensify Miller effect and provide capability to share Miller capacitor at multiple loops simultaneously. The proposed amplifier with corresponding frequency compensation is described symbolically while a circuit level implementation is performed via HSPICE circuit simulator and TSMC 0.18 μm CMOS technology. Based on simulation results, the proposed amplifier expresses a DC gain of 195 dB, a gain bandwidth product of 15.2 MHz, a phase margin of 90°, and a power dissipation of 570 μW.

A low power high area-efficiency NMOS LDO with fast adaptive bias

A low power consumption and fast transient response NMOS low dropout voltage regulator (LDO) with fast adaptive bias is proposed in this work. As a buffer between error amplifier and pass device in LDO, the symmetric flipped voltage follower could ensure stability and speed up the load transient response. In order to obtain better transient response performance and lower power consumption at quiescent state, an adaptive bias is used to generate adaptive current in different proportions, from load current to error amplifier and symmetric flipped voltage follower. The proposed LDO is designed in a 180 nm CMOS process with only 0.005 mm2 active area. Under the condition of typical process corner, the DC loop gain is at least 42.81 dB, and the phase margin ranges between 51.6° and 113.6°. Despite only 2.91μA quiescent current, the LDO with sub-microsecond settling time as low as 1ns at the edge of the load current change has little overshoot/undershoot.

Design of Two stage OTA with Optimised Compensation Capacitance

A two-stage operational transconductance amplifier is constructed and compared between 45nm and 180nm CMOS technology in this paper. To find the best design, the suggested operational amplifier is examined across a number of distinct parameters. With a supply voltage of 1.8V, it reaches a maximum gain of about 66 dB and a phase margin of 82°. A Cadence Virtuoso-based circuit simulator has been used to construct the suggested operational amplifier and the comparison is done. Keywords: OTA, Miller coupling capacitance, cadence virtuoso, Gain, output swing, power dissipation.

Dynamic Analysis and Active Stabilization of a Utility-Scale Grid-Connected Current-Source Inverter-Based PV System Considering Source Dynamics

This paper investigates the effects of the dynamic properties of a photovoltaic generator (PVG) on the stability of a grid-connected current-source inverter (CSI)-based photovoltaic system and presents a simple yet effective active compensator to ensure system stability. A detailed equivalent model of the PVG that considers the dynamic resistance, diffusion capacitance, series inductance, and dc cable resistance and inductance is used, and the effects of these parameters are assessed. It has been found that when the PVG operates in the constant-current region (CCR), the phase margin becomes negative in the control-to-input dynamics, which alters the stability of the dc-link current control. The change in the system dynamics when the operating point of the PVG shifts from the constant-voltage region (CVR) to CCR is verified through a detailed small-signal state-space model of the complete system. Furthermore, an active compensator is proposed to ensure stable dc-link current control operation at all operating points of the PVG. The influence of different control parameters on the integrated system dynamics is examined to determine the range of the control parameters required for stable operation. The performance of the proposed system under utility-grid fault, grid voltage parameter variation, weak grid, and changes in insolation level is also evaluated. Detailed nonlinear time-domain simulation results, using a typical utility-scale CSI-based PV system, validate the analytical results and the effectiveness of the proposed active stabilization under different operating conditions.

On the Minimum DC Link Capacitance in Practical PFC Rectifiers Considering THD Requirements and Load Transients

The article presents the analytical derivation of the minimum dc link capacitance in single-phase front ends with active power factor correction (PFC) without hold-up time requirements. Such systems typically employ boost-type rectifiers; operate under restricted total harmonic distortion (THD) of the grid-side current. Moreover, PFC rectifiers must be capable of tolerating step-like zero-to-rated load power variations. It is well known that these two constraints contradict each other, posing nontrivial design challenges. The revealed value of minimum capacitance is expressed by an explicit function of grid voltage and frequency, converter rated power, dc link voltage reference, and grid current THD and voltage loop phase margin set points. Experimental results validate the proposed methodology, closely matching corresponding analytical predictions.

Robustness Analysis of Distributed Kalman Filter for Estimation in Sensor Networks.

Motivated by the guaranteed stability margins of linear quadratic regulators (LQRs) and standard Kalman filter (KF) in the frequency domain, this article extends these results to the distributed Kalman-consensus filter (DKCF) for distributed estimation in sensor networks. In particular, we study the robustness margins of DKCF in two cases, one of which is based on the direct target observation while the other uses estimates from neighbor sensors in the network. The loop transfer functions of the two cases are established, and gain and phase margin robustness results are derived for both. The robustness margins of DKCF are improved compared to the single-agent KF. Furthermore, as communication topology varies in sensor networks, graph overall coupling strengths change. We also analyze the correlation between overall coupling strengths and the robustness margins of DKCF.

Robust modified partial internal model control for stable, unstable and integrating processes

ABSTRACT For open-loop stable processes, the internal model control (IMC) provides a simple and effective parameterisation of stabilising controllers. However, for unstable processes, it cannot be directly used for control system implementation. In this paper, a new unified approach for the IMC design is proposed for stable, unstable and integrating processes, using the modified IMC (m-IMC) structure in which an additional controller is introduced along with the basic IMC. Also, the partial IMC (PIMC) concept is utilised, wherein we write the plant as the summation of stable and unstable parts and consider only the stable part as the internal model. The combined approach is thereby referred to as modified partial IMC (m-PIMC). This paper presents a graphical method to obtain controller parameters for the proposed m-PIMC to satisfy the given gain margin () and phase margin () specifications. Further, stability boundary and robust boundary for the controller parameters are obtained which respectively give a set of all controller parameters stabilising the close loop and a set of all controller parameters ensuring robust stability. Seven different well-known standard stable, unstable and integrating process models are considered for the proposed m-PIMC design, and simulation examples are given for four selected plant models.

Research on Parameter Design and Control Method for Current Source Inverter–Fed IM Drive Systems

In the current source inverter (CSI)-fed inductor motor (IM) drive system, DC-bus inductance and AC-filter capacitance have a direct impact on the dynamic response speed, power quality and power density. In addition, due to the addition of filter capacitors, the mathematical model formed by the IM and capacitor is a third-order system, which increases the difficulty of parameter tuning for the control loop. To solve the above problems in the CSI, a DC-bus inductance design method based on current response speed and the ripple of the DC-link current and an AC-filter capacitance design method based on current utilization and filtering characteristics are presented. Then, the analytical expressions between the open-loop cut-off frequency, phase margin and the PI controller parameters of the current loop and speed loop are derived. Finally, an experimental platform is established to validate the proposed method.

A Time-Interleaved Charge Pump Internal Power Supply Generation Circuit

A charge pump internal power supply generation circuit for rail-to-rail operational amplifier is proposed, which combines a non-overlapping clock signal and a time-interleaved boost charge pump to achieve an internal power supply which is higher than the power supply voltage. A voltage follower is used to avoid glitch during time-interleaving switching. The charge pump internal power supply circuit is realized by 0.5μm CMOS process. The simulation results show that the internal power supply circuit of the charge pump can generate an internal power supply signal which is 1.8V higher than the power supply voltage. After applying this internal power supply to the PMOS input folded cascode operational amplifier, the operational amplifier achieves the rail-to-rail input, and the unity gain bandwidth and phase margin are stable.

Four‐stage CMOS operational transconductance amplifier: Compensated via double differential blocks

AbstractAdvancements in integrated circuits technology, force designers to adopt methods and approaches with posed limitations. Nowadays, multistage amplifiers are widely in demand due to high‐gain performance while avoiding placing transistors vertically in contrast with cascode structures. In this work, a four‐stage amplifier is investigated and frequency is compensated via a compensation network that includes two Miller capacitors at the outputs of differential blocks. So, using two Miller capacitors and sharing these capacitors common in four Miller loops, provide an opportunity to achieve acceptable frequency response regarding gain‐bandwidth product and phase margin. The proposed amplifier is modeled symbolically and simulated with the HSPICE circuit simulator with the help of 0.18 μm CMOS technology. According to the simulation results, the proposed approaches show superior performance compared with previously existing methods. Additionally, the sensitivity of the proposed amplifier against load and compensation capacitors expresses a stable and relatively fixed frequency response. Such a high gain amplifier with more than 180 dB as DC gain and 88° phase margin, is in great demand for realizing modulators and data converters.

Imaging features of intraductal tubulopapillary neoplasm of the pancreas and its differentiation from conventional pancreatic ductal adenocarcinoma

Intraductal tubulopapillary neoplasms (ITPN) are rare pancreatic tumors (< 1% of exocrine neoplasms) and are considered to have better prognosis than classical pancreatic ductal adenocarcinoma (PDAC). The present study aimed to evaluate imaging features of ITPN in computed tomography (CT) and magnetic resonance (MR) imaging. We performed monocentric retrospective analysis of 14 patients with histopathologically verified ITPN, operated in 2003–2018. Images were available for 12 patients and were analysed independently by two radiologists, blinded to reports. Imaging features were compared to a matched control group consisting of 43 patients with PDAC, matched for sex and age. Histopathologic analysis showed invasive carcinoma component in all ITPN patients. CT-attenuation values of ITPN were higher in arterial and venous phases (62.3 ± 14.6 HU and 68 ± 15.6 HU) than in unenhanced phase (39.2 ± 7.9 HU), compatible with solid lesion enhancement. Compared to PDAC, ITPN lesions had significantly higher HU-values in both arterial and venous phases (arterial and venous phases, p < 0.001). ITPN were significantly larger than PDAC (4.1 ± 2.0 cm versus 2.6 ± 0.84 cm, p = 0.021). ITPN lesions were more often well-circumscribed (p < 0.002). Employing a multiple logistic regression analysis with forward stepwise method, higher HU density in the arterial phase (p = 0.012) and well-circumscribed lesion margins (p = 0.047) were found to be significant predictors of ITPN versus PDAC. Our study identified key imaging features for differentiation of ITPN and PDAC. Isodensity or moderate hypodensity and well-circumscribed margins favor the diagnosis of ITPN over PDAC. Being familiar with CT-features of these rare pancreatic tumors is essential for radiologists to accelerate the diagnosis and narrow the differentials.