Phase-locked Loop Research Articles

Discrete-Time Position Sensorless Current Control for Permanent Magnet Synchronous Motors With an Accuracy-Improved Phase-Locked Loop

Discrete-Time Position Sensorless Current Control for Permanent Magnet Synchronous Motors With an Accuracy-Improved Phase-Locked Loop

Robust and fast backbone tracking via phase-locked loops

Phase-locked loops are commonly used for shaker-based backbone tracking of nonlinear structures. The state of the art is to tune the control parameters by trial and error. In the present work, an approach is proposed to make backbone tracking much more robust and faster. A simple PI controller is proposed, and closed-form expressions for the gains are provided that lead to an optimal settling of the phase transient. The required input parameters are obtained from a conventional shaker-based linear modal test, and an open-loop sine test at a single frequency and level. For phase detection, an adaptive filter based on the LMS algorithm is used, which is shown to be superior to the synchronous demodulation commonly used. Once the phase has locked, one can directly take the next step along the backbone, eliminating the hold times. The latter are currently used for recording the steady state, and to estimate Fourier coefficients in the post-process, which becomes unnecessary since the adaptive filter yields a highly accurate estimation at runtime. The excellent performance of the proposed approach is demonstrated for a doubly clamped beam undergoing bending–stretching coupling leading to a 20 percent shift of the lowest modal frequency. Even for fixed control parameters, designed for the linear regime, only about 100 periods are needed per backbone point, also in the nonlinear regime. This is much faster than what has been reported in the literature so far.

On the equivalence between steady-state Kalman filter and DPLL

Fundamental results in the literature showed that a class of Kalman filters (KF) converges to a digital phase lock loop (DPLL) structure. Results were proved for second- and third-order KFs. We extend these results to KFs of any order and derive in closed form the equivalent loop filter constants as a linear combination of the steady-state Kalman gains. We also give the inverse relation. Both closed-form relations involve Stirling numbers of the first or second kind. We implement both filters in a global navigation satellite system (GNSS) receiver and illustrate their equivalence with real-world data. These extended theoretical results provide a deeper understanding of the equivalence between KF and DPLL and may be of practical interest in highly dynamic scenarios to design and tune tracking filters.

A Practicable Optoelectronic Oscillator with Ultra-Low Phase Noise

In this paper, an optoelectronic oscillator (OEO) with ultra-low phase noise and high stability based on the injection-locked and phase-locked loop is proposed. In theory, the injection-locked frequency range of the injection signal is studied based on the phase dynamics equation, and the phase noise performance of the injection-locked OEO is analyzed. The role of the phase-locked loop on the frequency stability of the OEO is analyzed based on the phase-locked loop transfer function. In addition, this paper builds an injection-locked OEO based on a phase-locked loop. The injection-locked signal is the high-frequency output of the multiplication crystal oscillator (MCO). At the same time, this MCO synchronously outputs a low-frequency signal, which is used as the reference signal of the phase-locked loop. The experimental results show that the proposed OEO output frequency is 10 GHz, and the phase noise is −89.25 dBc/Hz@100 Hz, −121.71 dBc/Hz@1 kHz, and −145.39 dBc/Hz@10 kHz; the side-mode suppression ratio is 80 dB; the frequency stability is 2.06 × 10−11@1 s, 9.03 × 10−11@10 s, 1.03 × 10−10@100 s, and 3.03 × 10−10@1000 s. Consistent with the theoretical analysis results, the solution takes into account the frequency stability, side-mode suppression ratio, and phase noise performance. The simple structure is more advantageous in practical applications.

Parameter identification of PLL for grid‐connected inverter based on parameter sensitivity analysis

AbstractUnder the condition of weak grid, the phase‐locked loop (PLL) is one of the main reasons for the sub‐synchronous oscillation of the grid‐connected inverter. Therefore, it is necessary to identify the PLL parameters of the grid‐connected inverter for the analysis of the inverter operating performance. This paper uses the sequence impedance model and measured impedance data of grid‐connected inverter to construct the identification function for parameter identification of PLL, and the function is calculated by particle swarm optimization algorithm to overcome the nonlinear problem of sequence impedance model. In addition, the identification frequency band is selected based on PLL parameter sensitivity to improve the parameter identification accuracy under the same impedance measurement error. At different frequencies, the positive correlation between the sensitivity of the PLL parameters and the identification accuracy is proven to determine the definite frequency band for PLL parameter identification of grid‐connected inverter. Finally, the feasibility and effectiveness of the above research are verified by simulation and semi‐physical experiments.

Highly stable fiber-based photonic delay line with large and tunable delay.

A stable photonic delay line with large and tunable delay is essential for large-distance simulation, beamforming, and diverse photonic signal processing applications. Here, we demonstrate a fiber-based tunable photonic delay line (TPDL) with a maximum delay of 905 µs. Its environmental-related delay jitter is compensated for by a homodyne phase-locked loop (PLL). Precise delay tuning is realized by changing the phase of the reference with a minimum tuning step of 0.5 ps without breaking its locking state. The demonstrated delay line shows exceptional stability, as indicated by an overlapping Allan deviation (ADEV) of 2.06 × 10-17 at the averaging time of 1000 s and the delay jitter below 20 fs. Its high stability, wide delay range, wideband characteristics, and precise tunability make the TPDL an ideal photonic delay line for the above-mentioned applications.

An Efficient DC-AC Power Integration Model for Single-Phase Systems, Simulated in MATLAB

In the face of growing clean energy demands, this study presents a model for integrating Direct Current (DC) sources into the existing Alternating Current (AC) grid. The model is based on a single-phase system where a DC source is added. A converter, designed using the synchronous reference frame, is proposed to address integration issues. This converter allows for the control of both active and reactive power using a dq reference frame. A Proportional-Integrator (PI) controller is chosen for this purpose. To generate the necessary operational references, a Phase-Locked Loop (PLL) is used. An LCL filter is also incorporated based on its performance quality. The entire model is simulated in MATLAB, and the output obtained confirms the model’s ability to control both active and reactive power when integrating DC with AC and T. This work significantly contributes to the efforts of integrating clean energy into our existing grid systems.

Design of an Electromagnetic Micro Mirror Driving System for LiDAR.

Electromagnetic micro mirrors are in great demand for light detection and ranging (LiDAR) applications due to their light weight and low power consumption. The driven frequency of electromagnetic micro mirrors is very important to their performance and consumption. An electromagnetic micro mirror system is proposed in this paper. The model of the system was composed of a micro mirror, an integrated piezoresistive (PR) sensor, and a driving circuit was developed. The twisting angle of the mirror edge was monitored by an integrated PR sensor, which provides frequency feedback signals, and the PR sensor has good sensitivity and linearity in testing, with a maximum of 24.45 mV/deg. Stable sinusoidal voltage excitation and frequency tracking was realized via a phase-locked loop (PLL) in the driving circuit, with a frequency error within 10 Hz. Compared with other high-cost solutions using PLL circuits, it has greater advantages in power consumption, cost, and occupied area. The mechanical and piezoresistive properties of micro mirrors were performed in ANSYS 19.2 software. The behavior-level models of devices, circuits, and systems were validated by MATLAB R2023a Simulink, which contributes to the research on the large-angle deflection and low-power-consumption drive of the electromagnetic micro mirror. The maximum optical scan angle reached 37.6° at 4 kHz in the behavior-level model of the micro mirror.

Research on Clock Synchronization of Data Acquisition Based on NoC

Data acquisition based on network-on-chip (NoC) technology is a high-sampling-rate data acquisition scheme using low-sampling-rate analog–digital conversion (ADC) chips. It has the characteristics of multi-task parallel communication, being global asynchronous, local synchronous clock distribution, high throughput, low transmission latency, and strong scalability. High-speed data acquisition is realized through the combination of an on-chip network and time-interleaved data acquisition technology. In the time-interleaved sampling technique, the precision of clock synchronization directly affects the precision of sampling. Based on the proposed NOC data acquisition scheme, an improved White Rabbit clock synchronization protocol is applied to high-speed data acquisition to achieve high-precision synchronization of multi-channel time-interleaved sampling clocks. Firstly, the offset of the master clock and slave clock is determined by the PTP protocol, and the offset is corrected to achieve rough synchronization between the master clock and slave clock. Secondly, a digital dual-mixer time difference (DDMTD) is used to measure the phases of the master and slave clocks. After that, the phase of the slave clock is corrected through the dynamic phase-shift function of the clock’s phase-locked loop (PLL). Finally, according to the simulation results in Modelsim, the average absolute error of a TI-ADC sampling clock can be less than 20 ps.

Design of a high-speed MCML D-Latch at 0.6 V in 45 nm CMOS technology

Metal oxide semiconductor (MOS) current mode logic (MCML) is generally preferred for high-speed circuit design. In this paper, a novel low voltage folded (LVF) MCML D-Latch is designed. The existing topologies of the MCML D-Latch consume more power and operate at 1 V. The proposed D-Latch can operate at 0.6V with better delay and power management. MCML circuits minimize delay and perform fast operations, hence it can be used in high-frequency applications. The proposed LVF MCML D–Latch is analyzed with the parameters such as power, delay, power delay product and output noise using cadence virtuoso in 45 nm complementary metal oxide semiconductor (CMOS) technology at a voltage of 0.6 V and a temperature of 27 °C. The proposed technique achieves 62.11% of power reduction, transient response speed improved by 51.23% and noise cancellation becomes 26.13% improvement over the existing circuit. It also achieves 96% of output swing which is more efficient compared to others. Finally, the parametric analysis is performed with different temperatures to verify the stability of the proposed circuit. From the simulated results, it is clear that the proposed LVF MCML D-Latch provides better performance in high-speed phase locked loop (PLL) applications.

Control algorithm for an island microgrid under DSTATCOM using a Third Order Sinusoidal Integrator (TOSSI) to improve power quality for a local nonlinear load

Energy delivery to end-user customers is critically dependent on the distribution system. The system must synchronize correctly during island operation while connected as a microgrid to provide better power quality. The consumer experiences distortion and uneven power quality during these activities, raising severe research concerns. In order to mitigate the power quality issues at the end-user side, the modified Third Order Sinusoidal Integrator (TOSSI)-based DSTATCOM is the main topic of this research work. In order to instruct the DSTATCOM, the TOSSI receives feedback on phase, voltage, and frequency via the phase-locked loop (PLL) system. Through the use of the harmonic component of the load current, the enhanced TOSSI-based feedback enhances the dynamics of the distribution side. Enhancing DSTATCOM’s performance in distorted and unbalanced system circumstances is the aim of the suggested research. This work explores power factor correction and harmonic reduction in unbalanced and non-linear load settings utilizing modified TOSSI feedback, achieving an accuracy of 92%. The planned microgrid is modelled and simulated in MATLAB’s Simulink environment to demonstrate the importance of the suggested mitigation technique.

Fast synchronization with enhanced switching control for grid-tied single-phase square wave inverter using FPGA

Research on grid synchronization has been conducted worldwide by researchers in conjunction with the development of innovative technologies, such as dedicated short-range communication (DSRC) and cellular vehicle-to-everything (C-V2X). However, grid-connected inverters face several challenges, mainly the mismatch in voltage amplitude, frequency, and phase angle, as well as grid voltage disturbance and grid faults. Thus, the control algorithm of this research mainly focused on a half-cycle algorithm to design an enhanced digital switching control for fast synchronization using an FPGA. The control algorithm was developed based on zero-crossing detection (ZCD) and digital phase-locked loop (PLL) modeling techniques using the hardware description language (HDL) and a combination of digital logic blocks in Quartus II software, where the proposed switching was applied using the square-wave switching technique through a 300-watt full-bridge experimental prototype. The performance of the proposed technique was studied, where the total harmonic distortion (THD) for voltage and current resulted in a percentage reduction of 89.29% and 78.05% for voltage and current, respectively, after filter implementation. Also, the resulting signal synchronized in every half cycle and matched the voltage amplitude, frequency, and phase angle of the grid signal in 10 ms.

A 60-GHz Phase-Locked Loop Using Standing- Wave Oscillator for Clock Distribution in 2-D Phased-Array

A 60-GHz Phase-Locked Loop Using Standing- Wave Oscillator for Clock Distribution in 2-D Phased-Array

A 65-nm duty-cycle corrector achieving 10% to 90% duty-correction range with [formula omitted]0.86% duty-cycle error

This brief introduces a dual-loop analog duty-cycle corrector (DCC) designed to enhance the in-band phase noise performance of phase-locked loops (PLLs) by achieving precise duty cycle correction over a wide input duty cycle range. The proposed DCC incorporates a duty-cycle adjustor (DCA) within each loop, working in conjunction with a low-pass filter (LPF) and a duty-control amplifier to regulate the feedback control voltage. The feedback control voltage within each loop fine-tunes the timing delay of input pulse, ensuring that the output duty cycle of each loop is adjusted to 50%. Consequently, the proposed DCC demonstrates an expanded duty correction range. The proposed DCC was fabricated in a 65-nm standard CMOS process with an active area of 0.078 mm2. Measurement results validate the efficiency of the proposed DCC in correcting a wide range of input duty cycles (i.e., 10% to 90%) to an output duty cycle of 50% with a maximum duty cycle error of <0.86% for an input clock frequency ranging from 1 MHz to 100 MHz. To further showcase its effectiveness, the duty-corrected clock was supplied to a commercially available PLL (ADF4351). This demonstrated a noteworthy reduction of approximately 19 dB in reference spurs and a 10 dBc/Hz in the in-band phase noise.

Identification of secondary resonances of nonlinear systems using phase-locked loop testing

One unique feature of nonlinear dynamical systems is the existence of superharmonic and subharmonic resonances in addition to primary resonances. In this study, an effective vibration testing methodology is introduced for the experimental identification of these secondary resonances. The proposed method relies on phase-locked loop control combined with adaptive filters for online Fourier decomposition. To this end, the monotonic evolution of the phase lag around secondary resonances is exploited for their identification. The method is demonstrated using two systems featuring cubic nonlinearities, namely a numerical Duffing oscillator and a physical experiment comprising a clamped–clamped thin beam. The obtained results highlight that the control scheme can accurately characterize secondary resonances as well as track their backbone curves. A particularly salient feature of the developed algorithm is that, starting from the rest position, it facilitates an automatic and smooth dynamic state transfer toward one point of a subharmonic isolated branch, hence, inducing branch switching experimentally.

Sensorless fuzzy control algorithm for permanent magnet synchronous motor based on particle swarm optimization parameter identification and harmonic extraction

ABSTRACT In sensorless control of permanent magnet synchronous motor (IPMSM) with sliding mode observer, the problem of parameter robustness and poor stability seriously affects the control effect of sensorless operation. Therefore, a fuzzy sliding mode observer (SMO) phaselocked loop (PLL) combining particle swarm optimization (PSO) parameter identification and recursive least squares adaptive linear (RLS-Adaline) harmonic extractor is proposed. First, the fuzzy controller is used to process the control parameters of the sliding mode observer and the phaselocked loop. Secondly, the RLS-Adaline harmonic extractor is used to effectively filter the higher harmonic component of the back electromotive force (EMF), thus significantly improving the sensorless control effect. Thirdly, the PSO algorithm is used to identify the parameters of the motor, and the effect of parameter identification is judged by the performance index. The experimental results show that the proposed control method can effectively reduce the speed error and rotor position error.

Green energy solution for grid integrated solar PV system for water storage towers

In India, water storage towers are present almost everywhere, especially across small towns to rural areas. The storage tanks either utilize diesel powered or utility grid fed induction motor (IM) water pumps. The large spaces available with water storage towers can be utilized to plant solar PV panel for large storage towers water pumping operation, hence, making a switch from diesel or grid run storage towers to solar operated storage towers. This paper presents a robust control of grid integrated solar PV-based water pump system with efficient and smooth transition between standalone and grid interfaced modes. A smart DC link voltage control is presented for distributed generation system (DGS), which provides full control on DC link voltage for both modes of operation at all dynamic load conditions. An enhanced phase-locked loop (EPLL) control is utilized for grid source converter (GSC) in grid control operation, making it flexible to different grid scenarios and power quality. It works for harmonics suppression, load balancing and grid side converter control. An enhanced phase-locked loop (EPLL) is implemented for synchronization control algorithm, which provides an accurate estimation of voltage angle even during frequency ramps and exhibiting superior performance particularly in terms of robustness against DC offsets. The primary requirement for smooth operation of grid-tied solar PV system is effective power management between different sources. The issues of power management and power quality, are discussed in this work, and solutions are presented. The implemented control algorithms are tested successfully for dynamic solar insolation, varying load conditions, unbalance in load, sudden grid outage condition. The system appropriateness is validated by experimental results.

Coordination of SRF-PLL and Grid Forming Inverter Control in Microgrid with Solar PV and Energy Storage

Recently, there has been a huge advancement in renewable energy integration in power systems. Power converters with grid-forming or grid-following topologies are typically employed to link these decentralized power sources to the grid. However, because distributed generation has less inertia than synchronous generators, their use of renewable energy sources threatens the electrical grid’s reliability. Suitable control approaches for ensuring frequency and voltage stability in the grid-connected form of operation are established in this study, which offers dynamic, seamless power switching in the islanded mode of operation. In this research, effective Phase Locked Loop (PLL) techniques for grid-forming (GFM) and grid-following (GFL) converters are designed to achieve a smooth transition from grid-tied to islanded mode of operation. In this work, PLL configurations are implemented while considering the active and reactive power, frequency, voltage, and current parameters of the system, and ensuring voltage and frequency stability. The simulation results in a microgrid network that ensures a smooth transition of power transfer while switching between modes of operation, and supports the voltage and frequency stability of the system.

Broadband High-Linear FMCW Light Source Based on Spectral Stitching

The key to realizing a high-performance frequency-modulated continuous wave (FMCW) laser frequency-sweeping light source is how to extend the frequency-swept bandwidth and eliminate the effect of nonlinearity. To solve these issues, this paper designs a broadband high-linear FMCW frequency-sweeping light source system based on the combination of fixed temperature control and digital optoelectronic phase-locked loop (PLL), which controls the temperatures of the two lasers separately and attempts to achieve the coarse spectral stitching based on a time-division multiplexing scheme. Furthermore, we uses the PLL to correct the frequency error more specifically after the coarse stitching, which achieves the spectrum fine stitching and, meanwhile, realizes the nonlinearity correction. The experimental results show that our scheme can successfully achieve bandwidth expansion and nonlinearity correction, and the sweeping bandwidth is twice as much as that of the original single laser. The full-width half-maximum (FWHM) of the FMCW output is reduced from 150 kHz to 6.1 kHz, which exhibits excellent nonlinear correction performance. The relative error of the FMCW ranging system based on this frequency-swept light source is also reduced from 1.628% to 0.673%. Therefore, our frequency-swept light source with excellent performance has a promising application in the FMCW laser ranging system.

A Novel Approach to Managing System-on-Chip Sub-Blocks Using a 16-Bit Real-Time Operating System

Embedded computers are ubiquitous in products across various industries, including the automotive and medical industries, and in consumer goods such as appliances and entertainment devices. These specialized computing systems utilize Systems on Chips (SoCs), devices that are made up of one or more main microprocessor cores. SoCs are augmented with sub-blocks that perform dedicated tasks to support the system. Sub-blocks contain custom logic or small-footprint microprocessors, depending upon their complexity, and perform support functions such as clock generation, device testing, phase-locked loop synchronization and peripheral management for interfaces such as a Universal Serial Bus (USB) or Serial Peripheral Interface (SPI). SoC designers have traditionally obtained sub-blocks from commercial vendors. While these sub-blocks have well-defined interfaces, their internal implementations are opaque. Without visibility of the specifics of the implementation, SoC designers are limited to the degree to which they can optimize these off-the-shelf sub-blocks. The result is that power and area constraints are dictated by the design of a third-party vendor. This work introduces a novel idea: using an open-source, small, multitasking, real-time operating system inside an SoC sub-block to manage multiple processes, thereby conserving code space. This OS is TurbOS, a new operating system whose primary goal is to provide the highest performance using the least amount of space. It is written in the assembly language of a new pipelined 16-bit microprocessor developed at the University of Florida, the Turbo9. TurbOS is derived from and incorporates the design benefits of an existing operating system called NitrOS-9, and reduces the code size from its progenitor by nearly 20%. Furthermore, it is over 80% smaller than the popular FreeRTOS operating system. TurbOS delivers a rich feature set for managing memory and process resources that are useful in SoC sub-block applications in an extremely small footprint of only 3 kilobytes.