An improved single phase SPLL with DC and harmonics suppression

Abstract

This paper has proposed an improved single phase software phase lock loop (SPLL) with the ability of grid voltage DC and harmonics components suppression. An orthogonal signal generating method by frequency adaptive time delaying has been proposed to eliminate the grid voltage DC component, and frequency adaptive moving average filter (MAF) has been adopted to suppress the grid voltage harmonics. The loop transfer function has been deduced and the control parameter design of the MAF and SPLL controller has been detailed to balance between stability, overshoot and response time. Simulation experiments have shown that the proposed SPLL can correctly lock the fundamental frequency and phase even if there are large amounts of DC and high order harmonics components in the grid voltage.