Phase-locked Loop Structure Research Articles

Frequency Adaptive Grid Voltage Sensorless Control of LCL-Filtered Inverter Based on Extended Model Observer

This article presents a voltage sensorless control design for an LCL-filtered grid-connected inverter in discrete-time domain. The proposed scheme comprises a frequency adaptive current controller and a discrete current-type observer based on the linear quadratic regulator approach, which is robust against the harmonic distortion and frequency variation of grid voltage. A frequency adaptive observer is studied in detail by means of Lyapunov stability theory to ensure high accuracy tracking performance of estimated system variables and grid voltages under different grid conditions. Since the proposed method also generates precise grid frequency and phase angle to facilitate the synchronization task, the conventional phase-locked loop structure can be effectively eliminated. Simulation and experimental results are presented to validate the feasibility of the proposed control scheme.

High‐speed data acquisition of the reader of the SAW RFID system

The measurement of the echo time delays and phases of the surface acoustic wave (SAW) tag by the corresponding reader should be more accurate with the increase of the coding capacity, and the design of the high-speed data acquisition module (DAM) is the key factor for the improvement of the reader performance. Aiming at the large capacity SAW tag, which combines pulse time delay and phase coding, the radio-frequency (RF) band-pass sampling and digital quadrature demodulation scheme is utilised for the reader design. The design of the high-speed DAM includes the analysis, calculation and determination of the sampling frequency, the sampling clock design with cascaded phase-locked loop structure and the driver circuit design etc. Finally, the SAW RFID system is established, and the time delays and phases of the tag reflectors are tested. The measurement results show the effectiveness of the high-speed DAM of the reader.

Dual‐loop control of transfer delay based PLL for fast dynamics in single‐phase AC power systems

Phase-locked loop (PLL) is commonly utilised for AC power systems to detect phase and frequency. With the increasing use of small-scale distributed power generation, the technique becomes widely available for grid interconnection of renewable power source into single-phase AC distribution network. Through comprehensive analysis and design, this study proposed a new approach that includes dual independent control loops to enhance the transfer delay-based PLL capability in terms of speed and accuracy. The effectiveness and advantages of the proposed PLL structure are demonstrated by numerical simulation and verified by experimental test.

Nano CMOS Charge Pump for Readerless RFID PLL

Readerless RFID has become more significant for reliable wireless communication. The Phase Locked Loop (PLLs) are among the most crucial functional blocks in the Readerless RFID where the PLL performance greatly depend on the Charge Pump (CP). Conventional CP circuits suffer from current mismatching characteristics which generate phase offset and spurs in the PLL output signals. In order to overcome these problems, the CP current mismatch has to be minimized. An enhanced CP circuit with zero current mismatch is presented in this article adopting an ideal current mirror technique and an additional inverter to provide a rail-to-rail voltage. The post-layout simulation shows that the proposed CP maintain the steady current over a wide range of output voltage from 0.1-1.8 V consuming the substantially lower power of 0.178 µW. The CP circuit is designed in 130 nm CMOS process that operates at 1.8 V and the core occupies 17 x 59.5 μm 2 . The proposed CP will be a good solution for low voltage, high-frequency PLL structure which suffers from poor performances.

Hedge-Algebra-Based Phase-Locked Loop for Distorted Utility Conditions

This paper presents the first application of the hedge-algebra theory in the field of grid synchronization. For this purpose, an optimized hedge-algebra controller (HAC) is developed and incorporated within the three-phase phase-locked loop (PLL) with moving average filters (MAFs) inside its feedback loop. Optimized fuzziness parameters and linguistic rule base of the HAC are obtained by a genetic algorithm using the integral of absolute error as the performance index during optimization. Calculated optimal parameter values of the HAC depend on the most frequently occurring disturbance in the electric grid. Two different PLL structures are proposed, depending on the types of disturbances occurring in the electric grid. The first structure is the conventional synchronous reference frame PLL with the nonadaptive MAF (i.e., MAF without order adjustment), but with the PI/PID controller in the phase loop replaced by the developed HAC. Such PLL structure is suitable for all analyzed disturbance types, expect for step-changes in the grid frequency. The second PLL structure introduces the adaptive MAF (i.e., MAF with order adjustment) and a new feedback signal in the output stage of the controller to achieve zero steady-state error in the case of step-changes in the grid frequency. The disturbance rejection capability of the two developed PLLs with the HAC (HAC-PLLs) is tested separately and compared experimentally with the PID- and fuzzy-controller-based PLLs.

Robust Fault Ride-Through of Converter-based Generation during Severe Faults with Phase Jumps

As grid-connected converters are at risk of losing synchronism with the grid when exposed to extreme voltage sags, this might jeopardize the stability during a fault and a converter's ability to comply with fault ride-through requirements. This article investigates the synchronization stability of grid-tied converters during severe symmetrical faults with phase jumps. To achieve zero-voltage ride-through capability, a frozen phase-locked loop (PLL) structure can be employed to guarantee stability during faults. However, as the frozen PLL approach is unaware of frequency drifts and phase-angle jumps in the grid voltage, its performance during nonconstant frequency and phase is unknown. Therefore, this article investigates and provides new insight into how the frozen PLL performs during phase jumps and reveals whether phase compensation should be utilized to improve the converter response during a severe symmetrical fault. It is disclosed, that even though phase compensation can improve the injected currents during a fault situation including large phase jumps, a noncompensated frozen PLL can inherently ensure stability and allow for zero-voltage ride-through capability at an acceptable current injection. Furthermore, the robustness of the frozen PLL has been analyzed through a comprehensive simulation study where three test cases have been experimentally verified, which confirms the presented findings.

Simulation and investigations of a software implemented phase-locked loop with improved noise immunity

The improvement of noise immunity of a communication system is an effective way to increase the capacity of communication systems, which would provide more qualitative service for a larger number of users. This task can be solved by lowering the noise threshold of a phase-locked loop (PLL) in these systems if the dynamic properties of the device are preserved. The literature review indicates that such a device with improved noise immunity has already been implemented, but the effects of noise and modulation on its dynamic behavior were analyzed separately. This article is devoted to the analysis of the behavior of a digital firmware PLL under the simultaneous influence of noise and modulation of the input signal. The article depicts the structure of the classical digital PLL and its modifications and explains key differences between them. The simulation of the classical PLL with either absence or presence of noise at the device input was carried out. The simulation results show that the PLL is not able to detect all phase changes when the noise is present. Besides, the modified PLL has a wider working frequency range than the classical one under noisy conditions. The investigations of the PLL dynamic behavior with the simultaneous influence of random noise and Binary Phase Shift Keying (BPSK) modulated input signal was performed. The results of the research show that the duration of the transient processes during the processing of the BPSK modulated signal in the modified device is at least twice as low as that for the classical one. In addition, the number of errors during the signal detection increases faster for the classical PLL than for the modified one when the noise level rises. The use of the modified PLL in modern communication systems gives an opportunity to increase their capacity.

Adaptive Low-Pass Filter Based DC Offset Removal Technique for Three-Phase PLLs

The presence of dc offset in the inputs of a phase-locked loop (PLL) introduces fundamental frequency oscillations in the estimated quantities. Due to their low frequency in a synchronous reference frame, removal of these oscillations is a challenging task. Recent design studies of pre/in-loop filtering based advanced PLLs show that incorporation of dc offset removal in a filtering stage reduces the bandwidth of the PLL. This degrades the dynamic performance of the PLL and results in slower response time. To tackle this issue, a simple yet effective dc offset removal technique based on adaptive low-pass filters is introduced in this letter. The proposed technique can be applied as an add-on to any PLL structures without altering their design. Therefore, its application has a minimal effect on the dynamic performance of the PLL under study. The effectiveness of the proposed technique is evaluated experimentally by applying it to different PLL structures.

An Improved Frequency Measurement Method from the Digital PLL Structure for Single-Phase Grid-Connected PV Applications

The Phase Locked Loop (PLL) technique has been studied to obtain the phase and frequency information in grid-connected distributed generations for the sake of synchronizing the grid voltage and the inverter output current. In particular, the line frequency information, such as the anti-islanding function, is very important for the grid connection requirement. This paper presents a novel frequency measurement method from the digital PLL control structure for single-phase grid-connected PV applications. The conventional PLL controller uses the phase information to calculate the frequency of PV inverter output voltage after every line cycle and has shown a relatively low accuracy. This paper uses the angular frequency to directly measure the frequency after every line cycle. To verify the validity of the proposed method compared with the conventional method, a simulation was conducted. According to the simulation results, the measurement error of the proposed method is 80 times lower than the conventional one.

Flexible harmonic current compensation strategy applied in single and three-phase photovoltaic inverters

Non-linear loads connected to power system have increased considerably in the recent decades. Traditional generation based on hydro and thermal power plants cannot mitigate harmonic currents. However, due to the increased connection of photovoltaic into the power system, its power electronic converter can be used to perform ancillary services such as harmonic current compensation. This work presents a dynamic method based on the Second Order Generalized Integrator coupled with a phase locked loop structure to detect and compensate the most predominant harmonic current components from the power system. It is also presented an extension to detect multiple harmonics, according to the amplitude. Technical issues related with the harmonic current compensation strategy, and its implementation for both single and three-phase PV inverters are explored to demonstrate the functionality and efficiency of the method. The results show the harmonic current compensation being compensated by a PV inverter. Finally, a losses analysis were performed in the LCL filter. The magnetic and damping resistor losses are more impacted due to high harmonic current compensation.

Stability and Performance Assessment of Single-Phase <inline-formula> <tex-math notation="LaTeX">$T$ </tex-math> </inline-formula>/4 PLLs With Secondary Control Path in Current Sensorless Bridgeless PFCs

Bridgeless power factor correction (PFC) stages and the associated current shaping techniques require grid synchronization to ensure unity displacement power factor. In controllers with no current sensor, line current rebuilding algorithms are especially sensitive to synchronization issues. Phase-locked loops (PLLs) are used to synchronize the control of grid-connected converters, and may include a secondary control path to improve their dynamics in the case of grid disturbances. This paper presents linear models of $T$ /4 PLLs with secondary control paths. The $T$ /4 PLL structures are digitized and their performance evaluated. The stability conditions are determined. The PLL signal is utilized for current sensorless bridgeless PFCs, in the current estimation algorithm to reduce the estimation error, and as the reference in the current controller. The effect of the response of different PLLs on the PFC under grid disturbances is evaluated experimentally.

Network calibration method based on a Bayesian approach using frequency modulation communications for wireless systems over additive white Gaussian noise channel

Wireless sensor networks offer flexibility to monitor environmental conditions. However, in some hostile environments with changing propagation occurrences, it is challenging to guarantee a network free from systematic errors (biases), those errors can corrupt the data gathered from the network. The authors intend to address this problem using a Bayesian approach. This study presents a new Bayesian wireless network model based on a belief propagation algorithm over a noisy communication, to seek the calibration of the network for correlated sources. They set up a point-to-point communication model, consisting of a frequency modulation signal at the transmitter and a discrete-time phase-locked loop structure at the receiver over an additive white Gaussian noise channel. Then, they use a Bayesian approach to model the propagation of information, and analyse the noise impact on their system. The simulation results show significant improvement within a few time instants in the mean squared error of the sensors internal states. An evaluation in a noisy environment confirms the robustness of the proposed system.

Grid Voltage Estimation and Current Control of a Single-Phase Grid-Connected Converter Without Grid Voltage Sensor

This paper investigates the possibility of estimating the grid voltage and controlling a single-phase grid-connected converter without a dedicated grid voltage sensor. The main focus is given to current-controlled architectures which need phase-locked loops (PLL) for their operation. The grid voltage estimation method is proposed based on the active and reactive power delivered by the converter to the grid. In addition to the estimation of the grid voltage, the proposed method also generates the unit vectors and frequency information similar to a conventional PLL structure. The influence of various parameters like the dead time, equivalent loss resistance, and the filter inductance on the proposed estimation method is studied in details. Experimental results validate the feasibility of the proposed scheme.

A Hybrid Filtering Technique-Based PLL Targeting Fast and Robust Tracking Performance under Distorted Grid Conditions

In most grid-connected power converter applications, the phase-locked loop (PLL) is probably the most widespread grid synchronization technique, owing to its simple implementation. However, its phase-tracking performance tends to worsen when the grid voltage is under unbalanced and distorted conditions. Many filtering techniques are utilized to solve this problem, however, at the cost of slowing down the transient response. It is a major challenge for PLL to achieve a satisfactory dynamic performance without degrading its filtering capability. To tackle this challenge, a hybrid filtering technique is proposed in this paper. Our idea is to eliminate the fundamental frequency negative sequence (FFNS) and other harmonic sequences at the prefiltering stage and inner loop of PLL, respectively. Second-order generalized integrators (SOGIs) are used to remove FFNS before the Park transformation. This makes moving average filters (MAFs) eliminate other harmonics with a narrowed window length, which means the time delay that is caused by MAFs is reduced. The entire hybrid filtering technique is included in a quasi-type-1 PLL structure (QT1-PLL), which can provide a rapid dynamic behavior. The small-signal model of the proposed PLL is established. Based on this model, the parameter design guidelines targeting the fast transient response are given. Comprehensive experiments are carried out to confirm the effectiveness of our method. The results show that the settling time of the proposed PLL is less than one grid cycle, which is shorter than most of the widespread PLLs. The harmonic rejection capability is also better than other methods, under both nominal and adverse grid conditions.

Flying Start of a Permanent Magnet Wind Power Generator Based on a Discontinuous Converter Operation Mode and a Phase-Locked Loop

Flying start of a wind generator is a common requirement in wind turbine applications. This paper proposes a novel method for allowing the flying start of a permanent magnet generator (PMG). The proposed method is based on the discontinuous mode of operation of the converter and the phase-locked loop (PLL). During the discontinuous mode of operation, a series of zero-voltage pulses is applied to the generator, causing the occurrence of the short-circuit current, and thereby employing the PLL structure to estimate the rotor speed and angle. Also, a short-circuit current control structure with automatic adjustment of the reference value is proposed. The input signal to a PLL structure is adequately selected in order to enable a continuous mode of operation of the PMG. Simulation results demonstrate the applicability of the proposed method on the surface and interior PMGs, as well as on low- and high-power PMGs. The estimation accuracy does not depend on changes in the PMG parameters. The proposed method was implemented in a digital control system and experimentally verified on a 375 kW interior PMG. Experimental responses referring to the flying start of the PMG demonstrate the effectiveness of the proposed method.

Obtaining Performance of Type-3 Phase-Locked Loop Without Compromising the Benefits of Type-2 Control System

A phase-locked loop (PLL) is a closed-loop feedback control system that estimates the frequency as well as phase of an input signal. The most commonly deployed synchronization method in three-phase applications is a type-2 synchronous reference frame PLL. With pre/in-loop selective harmonic filtering stage, type-2 PLLs can obtain good detection speed, decent stability margins, and better disturbance rejection. However, it suffers from the finite steady-state phase error during ramp change in input signal frequency. To tackle this challenge type-3 PLLs have been developed recently, either by adding a feed-forward path to the PLL structure, or by using a second-order controller as the loop filter. However, recent analysis carried out of type-3 PLLs show that they aggravate stability problem and compromise the performance in terms of detection speed and disturbance rejection. A new concept of synchronization is proposed in this paper that obtains the performance of type-3 PLL but retains all the advantages associated with type-2 PLL. Extensive experimental results are provided to validate the proposed work.

Understanding of the Coherent Demodulation with Phase-Locked Loop

The phase-locked loop (PLL) technology is a very important technology in the communication field. With the development of electronic technology toward digitalization, the phase-locked processing of signal needs to be realized in digital way. Therefore, more and more attentions have been paid to the research and application of all digital phase-locked loops. This paper serves as an introduction about the basic background of PLL, the basic characteristics and structure of PLL, and the basic principles of modulation and demodulation. It provides a concise application about the basic principle and main design process of modulation and demodulation of FSK signal, which are realized by using phase-locked loop chip NE564.

Performance study of three synchronisation algorithms in renewable energy grid connected system

In grid connected applications, the efficiency of systems is strongly affected by the employed phase locked loop (PLL) strategy. This paper presents a comparative study of three PLL structures applied to a grid-connected renewable energy system with a nominal power of 7 MW. To select the suitable structure dedicated to previously mentioned application, we will evaluate the performance of the PLL techniques under distorted and unbalanced supply voltages. Several simulations test with a disturbed three phase utility grid using MATLAB-Simulink/SimpowerSystem are presented to valid the theoretical study.

New Configuration of a PLDRO with an Interconnected Dual PLL Structure for K-Band Application

A phase-locked dielectric resonator oscillator (PLDRO) is an essential component of millimeter-wave communication, in which phase noise is critical for satisfactory performance. The general structure of a PLDRO typically includes a dual loop of digital phase-locked loop (PLL) and analog PLL. A dual-loop PLDRO structure is generally used. The digital PLL generates an internal voltage controlled crystal oscillator (VCXO) frequency locked to an external reference frequency, and the analog PLL loop generates a DRO frequency locked to an internal VCXO frequency. A dual loop is used to ease the phase-locked frequency by using an internal VCXO. However, some of the output frequencies in each PLL structure worsen the phase noise because of the N divider ratio increase in the digital phase-locked loop integrated circuit. This study examines the design aspects of an interconnected PLL structure. In the proposed structure, the voltage tuning; which uses a varactor diode for the phase tracking of VCXO to match with the external reference) port of the VCXO in the digital PLL is controlled by one output port of the frequency divider in the analog PLL. We compare the proposed scheme with a typical PLDRO in terms of phase noise to show that the proposed structure has no performance degradation.

Improving the Design of MEMS INS-Aided PLLs for GNSS Carrier Phase Measurement under High Dynamics

The phase locked loop (PLL) bandwidth suffers a dilemma on carrier phase accuracy and dynamic stress tolerance in stand-alone global navigation satellite systems (GNSS) receivers. With inertial navigation system (INS) aiding, PLLs only need to tolerate aiding information error, instead of dynamic stress. To obtain accurate carrier phase under high dynamics, INS-aided PLLs need be optimally designed to reduce the impact of aiding information error. Typical micro-electro-mechanical systems (MEMS) INS-aided PLLs are implemented and tested under high dynamics. Tests using simulation show there is a step change in the aiding information at each integer second, which deteriorates the carrier phase accuracy. An improved structure of INS-aided PLLs is proposed to eliminate the step change impact. Even when the jerk is 2000 m/s3, the tracking error of the proposed INS-aided PLL is no more than 3°. Finally, the performances of stand-alone PLLs and INS-aided PLLs are compared using field tests. When the antenna jerk is 300 m/s3, the carrier phase error from the stand-alone PLLs significantly increased, while the carrier phase error from the MEMS INS-aided PLLs almost remained the same. Therefore, the proposed INS-aided PLLs can suppress tracking errors caused by noise and dynamic stress simultaneously under high dynamics.